NXP Semiconductors MWCT101 S Series, Reference Manual

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DDR mode (Hyperflash/HyperRAM) in individual flash mode , 8 cycles for Quad
Mode (SDR) instructions in Individual Flash Mode etc.
• Overhead due to clock domain crossing : 1 cycle.
The following table lists the number of clock cycles required to read the data from the
serial flash corresponding to the different settings of the QSPI_RBCT[WMRK] field:
Table 33-22. Access Duration Examples - Serial Flash side
QSPI_RBCT[WMR
K] setting
Num Bytes per
DMA Loop
1
Num SCKFx for 80MHz SCKFx Time duration of Flash data readout
for 80MHz SCKFx (~12.5ns period)
IFM
2
Quad IFM Quad DDR IFM Quad IFM Quad DDR
0 4 8 4 ~100ns ~50ns
1 8 16 8 ~200ns ~100ns
3 16 32 16 ~400ns ~200ns
7 32 64 32 ~800ns ~400ns
11 48 96 48 ~1200ns ~600ns
1. DMA Loop means one Minor loop completion which is equivalent to one Major Loop iteration.
2. Individual flash mode.
NOTE
The table figure represents ideal scenario, actual performance
will depend on how the system is integrated.
A complementary example would be when the watermark is set to be too high. In such a
case, the time taken by the DMA to read out the RX buffer entries should be smaller than
the time taken by the controller to push in the remaining entries in the buffer.
IPS Bus Side (data write):
The total number of bus cycles for each DMA Minor Loop completion is added from the
following components:
• Overhead for each minor loop, given by DMA controller: Assume 10 cycles
• Overhead due to clock domain crossing: Assume 2 cycles
• Number of bus clock cycles required for 16 bytes (128 bit write size): Assume 4
cycles (read/write sequence of DMA controller)
Note that the size of the minor loop is determined by the size of the
QSPI_TBCT[WMRK] field, therefore the overhead given above distributes among
(QSPI_TBCT[WMRK]+1) write accesses of 32 bit each.
Initialization/Application Information
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
910 NXP Semiconductors