NXP Semiconductors MWCT101 S Series, Reference Manual

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bit can be enabled before/after shifter data is sampled by configuring the
SHIFTCFG[SSTART], TIMCFG[TSTART] or SHIFTCFG[SSTOP], TIMCFG[TSTOP]
registers in the Shifter and Timer. Up to 16-bits of data can be compared using
SHIFTBUF[31:16] to configure the data to be matched and SHIFTBUF[15:0] to mask the
match result.
The Shifter Status Flag (SHIFTSTAT[SSF]) and any enabled interrupts or DMA requests
will set when a match occurs and matched data has been stored into the SHIFTBUF
register from the Shifter. The flag will clear when the matched data has been read from
the SHIFTBUF register.
The Shifter Error Flag (SHIFTERR[SEF]) and any enabled interrupts will set when an
attempt to store matched data into a full SHIFTBUF register occurs (buffer overrun) or
when a mismatch occurs on a start/stop bit check. The flag can be cleared by writing it
with logic 1.
48.4.2.4 Match Continuous Mode
When configured for Match Continuous mode (SHIFTCTL[SMOD]=Match Continuous),
the shifter will shift data in and continuously check for a match result whenever a shift
event is signalled by the assigned Timer. Up to 16-bits of data can be compared using
SHIFTBUF[31:16] to configure the data to be matched and SHIFTBUF[15:0] to mask the
match result.
The Shifter Status Flag (SHIFTSTAT[SSF]) and any enabled interrupts or DMA requests
will set when a match occurs. The flag will clear automatically as soon as there is no
longer a match between Shifter data and SHIFTBUF register.
The Shifter Error Flag (SHIFTERR[SEF]) and any enabled interrupts will set when a
match occurs. The flag will clear when there is a read from the SHIFTBUF register or it
written with logic 1.
48.4.3 Timer Operation
The FlexIO 16-bit timers control the loading, shifting and storing of the shift registers,
the counters load the contents of the compare register and decrement down to zero on the
FlexIO clock. They can perform generic timer functions such as generating a clock or
select output or a PWM waveform. Timers can be configured to enable in response to a
trigger, pin or shifter condition; decrement always or only on a trigger or pin edge; reset
in response to a trigger or pin condition; and disable on a trigger or pin condition or on a
timer compare. Timers can optionally include a start condition and/or stop condition.
Chapter 48 Flexible I/O (FlexIO)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1545