NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 636 / 1761

29.2.1 Block Diagram
The processor has a modified 32-bit Harvard bus architecture. Using a 32-bit address
space, low-order addresses (0x0000_0000 through 0x1FFF_FFFF) use the Processor
Code (PC) bus, and high-order addresses (0x2000_0000 through 0xFFFF_FFFF) use the
Processor System (PS) bus. As the bus names imply, normal operation has code accesses
on the PC bus and data accesses on the PS bus.
This device has been augmented with tightly-coupled memories for the PC and PS buses.
The memories include RAMs and caches. These local memories provide zero wait state
access to RAM and cacheable address spaces.
The local memory controller includes three memory controllers and their attached
memories:
• SRAM lower (SRAM_L) controller via the PC bus
• SRAM upper (SRAM_U) controller via the PS bus
• Cache memory controller via the PC bus
The local memory controller has the following 32-bit AMBA_ AHB buses:
• Two inputs are for the processor's modified Harvard buses − the Processor Code
(PC) and the Processor System (PS) buses.
• One input is for the "backdoor" port used by all other bus masters to access the
SRAM controller space.
• Two output ports are the CCM (Core Code Master) bus used for PC accesses that do
not hit the PC cache or SRAM_L or are non-cacheable and the CSM (Core System
Master) bus used for PS references that do not hit the SRAM_U.
Introduction
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
636 NXP Semiconductors