NXP Semiconductors MWCT101 S Series, Reference Manual, Page: 847 / 1761

33.4.2.5 Buffer1 Configuration Register (QuadSPI_BUF1CR)
This register provides the configuration for any access to buffer1. An access is routed to
buffer1 when the master port number of the incoming AHB request matches the
MSTRID field of BUF1CR. Any buffer "miss" leads to the buffer being flushed and a
serial flash transaction being triggered as per the sequence pointed to by the SEQID field.
Write:
• QSPI_SR[AHB_ACC] = 0
Address: 4007_6000h base + 14h offset = 4007_6014h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ADATSZ Reserved MSTRID
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * *
* Notes:
MSTRID field: See the module configuration for reset value. •
QuadSPI_BUF1CR field descriptions
Field Description
31–16
Reserved
This field is reserved.
15–8
ADATSZ
AHB data transfer size
Defines the data transfer size in 8 bytes of an AHB triggered access to serial flash. For example, a value
of 0x2 will set transfer size to 16 bytes. When ADATSZ = 0, the data size mentioned the sequence pointed
to by the SEQID field overrides this value. Software should ensure that this transfer size is not greater
than the size of this buffer.
7–4
Reserved
This field is reserved.
MSTRID Master ID. The ID of the AHB master associated with BUFFER1. Any AHB access with this master port
number is routed to this buffer. It must be ensured that the master IDs associated with all buffers must be
different.
33.4.2.6 Buffer2 Configuration Register (QuadSPI_BUF2CR)
This register provides the configuration for any access to buffer2. An access is routed to
buffer2 when the master port number of the incoming AHB request matches the
MSTRID field of BUF2CR. Any buffer "miss" leads to the buffer being flushed and a
serial flash transaction being triggered as per the sequence pointed to by the SEQID field.
Write:
• QSPI_SR[AHB_ACC] = 0
Chapter 33 Quad Serial Peripheral Interface (QuadSPI)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 847