NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 676 / 1761

Field Function
• if a 4 Kbyte Instruction Cache, then ICSZ = 0x04
• if an 8 Kbyte Instruction Cache, then ICSZ = 0x05
• if a 16 Kbyte Instruction Cache, then ICSZ = 0x06
• if a 32 Kbyte Instruction Cache, then ICSZ = 0x07
• if a 64 Kbyte Instruction Cache, then ICSZ = 0x08
23-16
ICWY
Level 1 Instruction Cache Ways
This read-only field provides the number of cache ways for the Instruction Cache. ICWY=0x00 indicates
not present.
15-8
DCSZ
Level 1 Data Cache Size
This read-only field provides an encoded value of the Data Cache size. The capacity of the memory is
expressed as Size [bytes] = 2
(8+DCSZ)
, where DCSZ is non-zero; a DCSZ = 0 indicates the memory is not
present.
• if no Data Cache, then DCSZ = 0x00
• if a 512 byte Data Cache, then DCSZ = 0x01
• if a 1 Kbyte Data Cache, then DCSZ = 0x02
• if a 2 Kbyte Data Cache, then DCSZ = 0x03
• if a 4 Kbyte Data Cache, then DCSZ = 0x04
• if an 8 Kbyte Data Cache, then DCSZ = 0x05
• if a 16 Kbyte Data Cache, then DCSZ = 0x06
• if a 32 Kbyte Data Cache, then DCSZ = 0x07
• if a 64 Kbyte Data Cache, then DCSZ = 0x08
7-0
DCWY
Level 1 Data Cache Ways
This read-only field provides the number of cache ways for the Data Cache. DCWY=0x00 indicates not
present.
30.4.2.15 Processor 0 Configuration Register 1 (CP0CFG1)
30.4.2.15.1 Offset
Register Offset
CP0CFG1 34h
30.4.2.15.2 Function
The CP0CFG1 register provides information on CPU0 Level 2 cache (if present).
Access: Privileged read-only
NOTE
Reset values for the Processor 0 Configuration Register 1:
• CP0CFG1 = 0x00000000
MSCM Memory Map/Register Definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
676 NXP Semiconductors