NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 487 / 1761

23.2.2.6 Stop mode acknowledge error (SACKERR)
The Stop mode acknowledge error (SACKERR) reset is generated if the core attempts to
enter Stop mode, but not all modules acknowledge stop mode within (2^16 +1
(corresponding to 0.5s)) cycles of the LPO128K_CLK.
A module might not acknowledge the entry to Stop mode if an error condition occurs.
The error can be caused by a failure of an external clock input to a module.
The RCM_SRS[SACKERR] bit is written to 1 to indicate this reset source.
23.2.2.7 Software reset (SW)
The SYSRESETREQ bit in the NVIC application interrupt and reset control register can
be written to 1 to force a software reset. (See
Arm's NVIC documentation for the full
description of the register fields, especially the VECTKEY field requirements.) Writing 1
to SYSRESETREQ generates a software reset request. This reset forces a system reset of
all major components except for the debug module. A software reset causes the MCU to
write 1 to
RCM_SRS[SW] field.
23.2.2.8 Lockup reset (LOCKUP)
The LOCKUP gives an immediate indication of seriously errant kernel software. This is
the result of the core being locked because of an unrecoverable exception following the
activation of the processor’s built in system state protection hardware.
The LOCKUP condition causes a system reset and also causes the MCU to write 1 to
RCM_SRS[LOCKUP] field. See Arm Cortex-M4 Devices Generic User Guide for details
on 'lockup' event.
23.2.2.9 MDM-AP system reset request
Writing 1 to the system reset request field in the MDM-AP control register initiates a
system reset. This is the primary method for resets via the JTAG/SWD interface. The
system reset is held until this field is written to 0.
Writing 1 to the core hold reset bit in the MDM-AP control register holds the core in
reset as the rest of the chip comes out of system reset.
Chapter 23 Reset and Boot
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 487