NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 596 / 1761

27.6.19.3 Diagram
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
P R
CGC
Reserved
0
PC S
0
W
Reset
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
27.6.19.4 Fields
Field Function
31
PR
Present
This bit shows whether the peripheral is present on this device.
0b - Peripheral is not present.
1b - Peripheral is present.
30
CGC
Clock Gate Control
This read/write bit enables the interface clock for the peripheral, allowing access to the module's
registers. It also controls whether the clock selection and divider options can be modified.
0b - Clock disabled. The current clock selection and divider options are not locked and can be
modified.
1b - Clock enabled. The current clock selection and divider options are locked and cannot be
modified.
29
—
This read-only bit field is reserved. This bit can change values but is a don't-care.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
Peripheral Clock Source Select
This read/write bit field is used for peripherals that support various clock selections.
This field can be written only when the clock is disabled (CGC = 0).
000b - Clock is off.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5
110b - Clock option 6
Table continues on the next page...
PCC register descriptions
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
596 NXP Semiconductors