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NXP Semiconductors MWCT101 S Series, Reference Manual

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The following table shows the channel decoding in both functional mode and trigger
mode. Other cases not listed in the table are illegal.

Table 39-7. CMP channel decoding in functional mode and trigger mode

Mode

RRE

PSEL[

2:0]

MSEL[

2:0]

INPSE

L[1:0]

INNSE

L[1:0]

FXMP

FXMX

CH[2:0

]

CHNx

INP

INN

CMP

Behavior

Functional
Mode

0

x

1

0~7

0

1

x

x

x

DAC

Channel
decoded
from
MSEL[2:0]

Channel 0~7
can be
compared
with DAC

0~7

x

1

0

x

x

x

Channel
decoded
from
PSEL[2:0]

DAC

Channel 0~7
can be
compared
with DAC

0~7

0~7

1

1

x

x

x

Channel
decoded
from
PSEL[2:0]

Channel
decoded
from
MSEL[2:0]

Channel 0~7
can be
compared
with channel
0~7

2

Trigger
Mode

1

x

x

0

1

0

x

0~7

DAC

Channel
sweep
(CHN

x

)

Channel 0~7
can be swept
with DAC

x

x

1

0

1

x

0~7

Channel
sweep

(CHN

x

)

DAC

Channel 0~7
can be swept
with DAC

x

x

1

1

0

0~7

0~7

Channel
fixed by
FXMXCH[
2:0]

Channel
sweep
(CHN

x

)

Channel 0~7
can be swept
with a fixed
channel
(0~7)

3

x

x

1

1

1

0~7

0~7

Channel
sweep
(CHN

x

)

Channel
fixed by
FXMXCH[
2:0]

Channel 0~7
can be swept
with a fixed
channel
(0~7)

3

1. "x" means "do not care".
2. PSEL should not be set the same as MSEL.
3. Channel in the sweep side should not be the same as the fixed side.

Trigger mode

MWCT101xS Series Reference Manual, Rev. 3, 07/2019

1082

NXP Semiconductors

Summary of Contents for MWCT101 S Series

Page 1: ...MWCT101xS Series Reference Manual Supports MWCT1014SFxxx MWCT1015SFxxx MWCT1016SFxxx Document Number MWCT101XSFRM Rev 3 07 2019...

Page 2: ...MWCT101xS Series Reference Manual Rev 3 07 2019 2 NXP Semiconductors...

Page 3: ...es Cautions and Warnings 47 1 5 2 Numbering systems 47 1 5 3 Typographic notation 48 1 5 4 Special terms 48 Chapter 2 Introduction 2 1 Overview 51 2 2 MWCT101xS Series introduction 51 2 3 Feature summ...

Page 4: ...ased bit band regions 68 Chapter 4 Signal Multiplexing and Pin Assignment 4 1 Introduction 71 4 2 Functional description 71 4 3 Pad description 72 4 4 Default pad state 73 4 5 Signal Multiplexing shee...

Page 5: ...2 1 Cortex M4 Structural Core Self Test SCST 91 6 2 2 ECC on RAM and flash memory 92 6 2 3 Power supply monitoring 92 6 2 4 Clock monitoring 93 6 2 5 Temporal protection 93 6 2 6 Operational interfere...

Page 6: ...ation MCM_PLAMC 107 8 3 3 Core Platform Control Register MCM_CPCR 109 8 3 4 Interrupt Status and Control Register MCM_ISCR 112 8 3 5 Process ID Register MCM_PID 115 8 3 6 Compute Operation Control Reg...

Page 7: ...161 10 1 5 Reset pin configuration 162 10 2 Introduction 162 10 3 Overview 162 10 3 1 Features 162 10 3 2 Modes of operation 163 10 4 External signal description 164 10 5 Detailed signal description 1...

Page 8: ...11 1 2 GPIO ports memory map 183 11 1 3 GPIO register reset values 184 11 2 Introduction 184 11 2 1 Features 184 11 2 2 Modes of operation 184 11 2 3 GPIO signal descriptions 185 11 3 Memory map and...

Page 9: ...scriptions 204 13 4 1 MPU Memory map 205 13 4 2 Control Error Status Register CESR 207 13 4 3 Error Address Register slave port n EAR0 EAR4 210 13 4 4 Error Detail Register slave port n EDR0 EDR4 211...

Page 10: ...ion information 237 14 1 2 Memory maps 237 14 2 Introduction 238 14 2 1 Features 238 14 2 2 General operation 238 14 3 Memory map register definition 239 14 3 1 AIPS register descriptions 239 14 4 Fun...

Page 11: ...97 16 1 1 Number of channels 297 16 2 Introduction 297 16 2 1 eDMA system block diagram 298 16 2 2 Block parts 298 16 2 3 Features 299 16 3 Modes of operation 301 16 4 Memory map register definition 3...

Page 12: ...373 17 1 2 Chip specific TRGMUX registers 377 17 2 Introduction 377 17 3 Features 377 17 4 Memory map and register definition 378 17 4 1 TRGMUX register descriptions 378 Chapter 18 External Watchdog...

Page 13: ...1 Overview 431 19 2 2 Features 433 19 3 EIM register descriptions 433 19 3 1 EIM Memory map 434 19 3 2 Error Injection Module Configuration Register EIMCR 434 19 3 3 Error Injection Channel Enable reg...

Page 14: ...21 Watchdog timer WDOG 21 1 Chip specific WDOG information 453 21 1 1 WDOG clocks 453 21 1 2 WDOG low power modes 453 21 1 3 Default watchdog timeout 454 21 1 4 Watchdog Timeout Reaction 454 21 2 Int...

Page 15: ...uction 473 22 2 1 Features 473 22 2 2 Block diagram 474 22 2 3 Modes of operation 474 22 3 Memory map and register descriptions 474 22 3 1 CRC register descriptions 474 22 4 Functional description 479...

Page 16: ...496 24 4 3 System Reset Status Register RCM_SRS 498 24 4 4 Reset Pin Control register RCM_RPC 501 24 4 5 Sticky System Reset Status Register RCM_SSRS 503 24 4 6 System Reset Interrupt Enable Register...

Page 17: ...CG_HCCR 541 26 3 7 SCG CLKOUT Configuration Register SCG_CLKOUTCNFG 543 26 3 8 System OSC Control Status Register SCG_SOSCCSR 545 26 3 9 System OSC Divide Register SCG_SOSCDIV 547 26 3 10 System Oscil...

Page 18: ...27 6 4 PCC FlexCAN0 Register PCC_FlexCAN0 572 27 6 5 PCC FlexCAN1 Register PCC_FlexCAN1 573 27 6 6 PCC FTM3 Register PCC_FTM3 575 27 6 7 PCC ADC1 Register PCC_ADC1 576 27 6 8 PCC FlexCAN2 Register PC...

Page 19: ...C_LPI2C1 612 27 6 31 PCC LPUART0 Register PCC_LPUART0 614 27 6 32 PCC LPUART1 Register PCC_LPUART1 615 27 6 33 PCC LPUART2 Register PCC_LPUART2 617 27 6 34 PCC FTM4 Register PCC_FTM4 619 27 6 35 PCC F...

Page 20: ...29 4 Functional Description 648 29 4 1 LMEM Function 648 29 4 2 SRAM Function 649 29 4 3 Cache Function 651 29 4 4 Cache Control 652 Chapter 30 Miscellaneous System Control Module MSCM 30 1 Chip spec...

Page 21: ...FTFC information 697 32 1 1 Flash memory types 698 32 1 2 Flash memory sizes 698 32 1 3 Flash memory map 708 32 1 4 Flash memory security 708 32 1 5 Power mode restrictions on flash memory programming...

Page 22: ...rite RWW 743 32 5 8 Flash program and erase 743 32 5 9 FTFC command operations 743 32 5 10 Margin read commands 750 32 5 11 Flash command descriptions 751 32 5 12 Security 777 32 5 13 Cryptographic Se...

Page 23: ...Access 833 33 4 2 Peripheral Bus Register Descriptions 834 33 4 3 Serial Flash Address Assignment 878 33 5 Flash memory mapped AMBA bus 879 33 5 1 AHB Bus Access Considerations 880 33 5 2 Memory Mapp...

Page 24: ...upported read modes 922 33 12 3 Data Strobe DQS sampling method 925 33 13 Data Input Hold Requirement of Flash 928 Chapter 34 Power Management 34 1 Introduction 929 34 2 Power modes description 929 34...

Page 25: ...6 Power Mode Status register SMC_PMSTAT 950 35 4 Functional description 951 35 4 1 Power mode transitions 951 35 4 2 Power mode entry exit sequencing 952 35 4 3 Run modes 955 35 4 4 Stop modes 957 35...

Page 26: ...Interleaved Channels 973 37 5 ADC internal supply monitoring 974 37 6 ADC Reference Options 974 37 7 ADC Trigger Sources 975 37 7 1 PDB triggering scheme 977 37 7 2 TRGMUX trigger scheme 978 37 8 Trig...

Page 27: ...gister OFS 1012 38 4 11 USER Offset Correction Register USR_OFS 1013 38 4 12 ADC X Offset Correction Register XOFS 1014 38 4 13 ADC Y Offset Correction Register YOFS 1015 38 4 14 ADC Gain Register G 1...

Page 28: ...isters RAA RZ 1035 38 5 Functional description 1037 38 5 1 Clock select and divide control 1037 38 5 2 Voltage reference selection 1038 38 5 3 Hardware trigger and channel selects 1038 38 5 4 Conversi...

Page 29: ...indowed Resampled mode 6 1064 39 7 7 Windowed Filtered mode 7 1065 39 8 Memory map register definitions 1066 39 8 1 CMP Control Register 0 CMPx_C0 1066 39 8 2 CMP Control Register 1 CMPx_C1 1070 39 8...

Page 30: ...x_SC 1098 40 3 2 Modulus register PDBx_MOD 1101 40 3 3 Counter register PDBx_CNT 1101 40 3 4 Interrupt Delay register PDBx_IDLY 1102 40 3 5 Channel n Control register 1 PDBx_CHnC1 1102 40 3 6 Channel...

Page 31: ...TM 41 1 Chip specific FTM information 1119 41 1 1 Instantiation Information 1119 41 1 2 FTM Interrupts 1120 41 1 3 FTM Fault Detection Inputs 1120 41 1 4 FTM Hardware Triggers and Synchronization 1121...

Page 32: ...dified Combine PWM Mode 1216 41 5 11 Complementary Mode 1219 41 5 12 Registers updated from write buffers 1221 41 5 13 PWM synchronization 1222 41 5 14 Inverting 1238 41 5 15 Software Output Control M...

Page 33: ...41 7 3 Channel n Interrupt 1291 41 7 4 Fault Interrupt 1291 41 8 Initialization Procedure 1292 Chapter 42 Low Power Interrupt Timer LPIT 42 1 Chip specific LPIT information 1295 42 1 1 Instantiation I...

Page 34: ...eatures 1336 43 2 2 Modes of operation 1336 43 3 LPTMR signal descriptions 1337 43 3 1 Detailed signal descriptions 1337 43 4 Memory map and register definition 1337 43 4 1 LPTMR register descriptions...

Page 35: ...r clocking and reset 1361 44 4 2 Time counter 1362 44 4 3 Compensation 1363 44 4 4 Time alarm 1364 44 4 5 Update mode 1364 44 4 6 Register lock 1364 44 4 7 Interrupt 1365 Chapter 45 Low Power Serial P...

Page 36: ...Features 1411 46 2 2 Block Diagram 1413 46 2 3 Modes of operation 1413 46 2 4 Signal Descriptions 1413 46 2 5 Wiring options 1414 46 3 Memory Map and Registers 1415 46 3 1 LPI2C register descriptions...

Page 37: ...scription 1502 47 4 5 Additional LPUART functions 1508 47 4 6 Infrared interface 1510 47 4 7 Interrupts and status flags 1511 47 4 8 Peripheral Triggers 1512 Chapter 48 Flexible I O FlexIO 48 1 Chip s...

Page 38: ...7 I2S Slave 1561 Chapter 49 FlexCAN 49 1 Chip specific FlexCAN information 1563 49 1 1 Instantiation information 1563 49 1 2 Reset value of MDIS bit 1563 49 1 3 FlexCAN external time tick 1564 49 1 4...

Page 39: ...nsmit process 1657 49 5 2 Arbitration process 1659 49 5 3 Receive process 1662 49 5 4 Matching process 1664 49 5 5 Receive process under Pretended Networking mode 1669 49 5 6 Move process 1673 49 5 7...

Page 40: ...722 50 10 Core trace connectivity 1723 50 11 TPIU 1723 50 12 DWT 1724 50 13 Debug in low power modes 1724 50 13 1 Debug module state in low power modes 1725 50 14 Debug and security 1725 Chapter 51 JT...

Page 41: ...register 1732 51 4 4 Boundary scan register 1732 51 5 Functional description 1733 51 5 1 JTAGC reset configuration 1733 51 5 2 IEEE 1149 1 2001 JTAG TAP 1733 51 5 3 TAP controller state machine 1733 5...

Page 42: ...MWCT101xS Series Reference Manual Rev 3 07 2019 42 NXP Semiconductors...

Page 43: ...fic WCT101xS derivative derivative device please refer to the respective Chip specific Module information 1 2 Organization This manual has two main sets of chapters 1 Chapters in the first set contain...

Page 44: ...not apply to these instances NOTE For eSCI_D thesinglewirefeaturedoesnot apply for TX RX viaPCSA3 becausethispad worksonly asan output 49 2 Introduction TheeSCI block isan enhanced SCI block with aLI...

Page 45: ...ts Access Reset value Section page 0 SWT Control Register SWT_CR 32 R W See section 34 4 1 1331 4 SWT Interrupt Register SWT_IR 32 R W 0000_0000h 34 4 2 1334 8 SWT Time out Register SWT_TO 32 R W See...

Page 46: ...bitrates with Core0 data for XBAR port 1 Core1 instruction 2 1 Core1 data 3 1 Nexus_3_1 9 Nexus_3_1 arbitrates with Core1 data for XBAR port 3 Table continues on the next page Sample Reference Manual...

Page 47: ...s Note Caution and Warning notices appear throughout this manual Each notice type alerts readers to a specific kind of information NOTE Notes convey information that may be tangential to a topic or th...

Page 48: ...ers and operators Fixed width type is also used for example code Instruction mnemonics and directives in text and tables are shown in all caps for example BSR SR SCM A mnemonic in brackets represents...

Page 49: ...lue Do not modify the default value of a reserved programming setting such as the reset value of a reserved register field Consider undefined locations in memory to be reserved w1c Write 1 to clear Re...

Page 50: ...Conventions MWCT101xS Series Reference Manual Rev 3 07 2019 50 NXP Semiconductors...

Page 51: ...llers based on the Arm Cortex M4F core They offer superior performance large memories and the most scalable peripherals in this class This product series provides up to 112 MHz CPU performance with DS...

Page 52: ...o compatible evaluation boards WCT Software Development Kit SDK including graphical configurability and WCT Design Studio software as well as broad support from IAR Systems Keil MDK and other partners...

Page 53: ...D flash emulated EEPROM 2 backup E Flash memory 4 KB additional FlexRAM supporting high endurance non volatile emulated EEPROM Flash memory controller cache Yes single speculative prefetch buffer onl...

Page 54: ...s with 8 pre triggers for each channel for ADC0 1 pulse out channel Programmable delay block 1 PDB1 2 ADC channel with 8 pre triggers for each channel for ADC1 1 pulse out channel Flexible timer FTM0...

Page 55: ...mode 112 MHz because this use case is not allowed to execute simultaneously The device need to switch to RUN mode 80 Mhz to execute CSEc Security or EEPROM writes erase 3 On this device NXP s system M...

Page 56: ...family does not integrate the Arm Core MPU which would concurrently monitor only core initiated memory accesses In this document the term MPU refers to NXP s system MPU 2 For the device specific sizes...

Page 57: ...Trigger mux TRGMUX Real time counter RTC FlexTimer 16 bit counter 8 channels External memory interface 12 bit SAR ADC 1 MSPS each FlexIO 8 pins configurable as UART SPI I2C I2S Low power I2C Debug tr...

Page 58: ...grouped into functional categories The following sections describe the modules assigned to each category in more detail Table 2 3 Module functional categories Module category Description Arm Cortex M4...

Page 59: ...SPI Low power Inter integrated circuit LPI2C Low power UART LPUART FlexIO FlexCAN Debug JTAG Controller JTAGC 2 7 1 Arm Cortex M4F Core Modules The following core modules are available on this device...

Page 60: ...pport Instrumentation Trace Macrocell ITM with software and hardware trace plus time stamping Flash Patch and Breakpoints FPB with ability to patch code and data from code space to system space Serial...

Page 61: ...eed value and optional feature to transpose input data and CRC result via transpose register 2 7 3 Memories and memory interfaces The following memories and memory interfaces are available on this dev...

Page 62: ...r other on chip peripherals Slow internal reference clock SIRC An internally generated 8 MHz clock which can be used as a clock source for other on chip peripherals System oscillator OSC The system os...

Page 63: ...y outputs or independent channels with independent outputs Deadtime insertion is available for each complementary pair Generation of hardware triggers Software control of PWM outputs Up to 4 fault inp...

Page 64: ...modes Low power Universal asynchronous receiver transmitters LPUART Asynchronous serial bus communication interface supporting LIN master and slave operation LPUART optionally remains functional in lo...

Page 65: ...The RAM is implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in the memory map See MWCT101xS_memory_map xlsx attached to this document for details Accesses to the SRAM_L and...

Page 66: ...itioned as 96 spaces each 4 KB in size and reserved for off platform modules AIPS Lite generates unique module enables for all 96 spaces 0x400F_F000 A 4 KB region for accessing the GPIO module This bl...

Page 67: ...Read after write sequence to guarantee required serialization of memory operations Step Action 1 Write the peripheral register 2 Read the written peripheral register to verify the write 3 Continue wi...

Page 68: ...0xE008_1FFF Reserved 0xE008_2000 0xE008_2FFF Cache Controller LMEM 0xE008_3000 0xE00F_EFFF Reserved 0xE00F_F000 0xE00F_FFFF Arm Core ROM Table1 allows auto detection of debug components 1 The Arm Cor...

Page 69: ...t band region 1 MB 32 MB Figure 3 2 Alias bit band mapping NOTE Each bit in a bit band region has an equivalent bit that can be manipulated through bit 0 in a corresponding long word in the alias bit...

Page 70: ...Aliased bit band regions MWCT101xS Series Reference Manual Rev 3 07 2019 70 NXP Semiconductors...

Page 71: ...rols the module specific pad settings pull up etc and the signal present on the external pin See PORT_PCR for the description of control signals For reset values per port see IO Signal Description Inp...

Page 72: ...O I O to external world do I Data coming from the core into the pad obe I Enable output driver pue I 0 Disable internal pullup or pulldown resistor 1 Enable internal pullup or pulldown resistor pus I...

Page 73: ...t requires open drain e g LPI2C LPUART single wire will work in open drain mode 4 4 Default pad state The default pad configurations out of reset are as follows For PTA4 PTA5 PTC4 and PTC5 the default...

Page 74: ...g specifies the priority for the input muxing where an input path is driven by more than one pad WCT101xS variant specific IO Signal Description Input Multiplexing sheets attached to the Reference Man...

Page 75: ...analog functionality once the analog module is configured to enable corresponding channel input For example PTA0 supports ADC0 channel 0 and CMP channel 0 By default the pad is disabled After ADC0 is...

Page 76: ...nippet of Input Muxing Table Figure 4 4 Input muxing table snippet The columns of the figure are briefly described below Destination Instance This field contains the instance name of the input path to...

Page 77: ...ption Input Multiplexing sheet s attached to the Reference Manual for pinout diagrams corresponding to available packages Chapter 4 Signal Multiplexing and Pin Assignment MWCT101xS Series Reference Ma...

Page 78: ...Pinout diagrams MWCT101xS Series Reference Manual Rev 3 07 2019 78 NXP Semiconductors...

Page 79: ...size of the 4 KB EEERAM is reduced by the space required to store the user keys The user key space effectively becomes un addressable space in the EEERAM For parts with key size 00 CSEc_PRAM access is...

Page 80: ...When flash memory security is active the SWD port cannot access the memory resources of the MCU Although most debug functions are disabled the debugger can write to the Flash Mass Erase in Progress bi...

Page 81: ...before attempting to actuate any SHE command Additionally during parallel secure boot any mode transition initiated by Core will be aborted and secure boot will proceed During parallel boot operation...

Page 82: ...ntegrity and authenticity In this use case The bootloader is protected by the secure boot process MACs stored in the bootloader provide integrity and authenticity of the related parts in flash memory...

Page 83: ...egal messages sent by ECUs Random number generation and checking protect against replay attacks Encryption protects against eavesdropping Random number generation checking and encryption ensure data i...

Page 84: ...The replacement or modification of ECU n will change its unique ID and or keys This use case shows how both changes are detected Figure 5 4 Component protection Security use case examples MWCT101xS S...

Page 85: ...er 2 FlexCAN triggers interrupt to core DMA 3 Transfer data to CSEc memory maximum 12 CAN messages of 8 bytes 16 byte CMAC 4 Trigger CSEc CMAC calculation verification 5 CSEc triggers interrupt to cor...

Page 86: ...0x06 0x00 0x01 CMD Word MAC Len MSG Len Length KeyID 0x06 0x00 0x01 CMD Word MAC Len MSG Len Length 3 4 5 6 Length CMD Word Length CMD Word Length CMD Word Length 13 12 11 10 9 8 14 20 19 18 17 16 15...

Page 87: ...figure desired number of keys and other parameters 2 Program code section in Pflash to be checked in secure boot 3 LOAD_KEY BOOT_MAC_KEY 4 CMD_BOOT_DEFINE to select the flavor of boot and size of data...

Page 88: ...Security programming flow example Secure Boot MWCT101xS Series Reference Manual Rev 3 07 2019 88 NXP Semiconductors...

Page 89: ...safety concept and possible safety mechanisms integrated in WCT101xS system level hardware or system level software as well as measures to reduce dependent failures Dynamic FMEDA inductive analysis e...

Page 90: ...require an ASIL B safety integrity level In general safety integrity is achieved by using and applying WCT101xS safety features as described in the Safety Manual The following diagram provides an ove...

Page 91: ...ache Mux System MPU 1 SWJ DP TPIU AHB AP PPB Arm Cortex M4F Core DSP FPU DWT FPB ITM NVIC AWIC S1 eDMA Clock Generation Power supply monitoring Clock monitoring System memory protection unit ECC on fl...

Page 92: ...ns and assumptions that should be fulfilled and verified by a user for the proper use of the SCST library for a Cortex M4 core 6 2 2 ECC on RAM and flash memory Error correcting codes are used to prot...

Page 93: ...at software is executing as planned and that the CPU is not stuck in an infinite loop External Watchdog Monitor EWM A redundant watchdog system for safety The EWM provides an independent output signal...

Page 94: ...ption in this Reference Manual see AIPS Lite Peripheral protection in safety concept see Safety Manual chapter 6 2 6 3 Register protection WCT101xS offers register protection for safety critical regis...

Page 95: ...esources to provide this support Digital inputs can be replicated to acquire safety critical inputs redundantly Safety critical digital outputs can always be written redundantly or in combination with...

Page 96: ...WCT101xS safety concept MWCT101xS Series Reference Manual Rev 3 07 2019 96 NXP Semiconductors...

Page 97: ...ted module Reference Full description Arm Cortex M4F core Arm Cortex M4F Technical Reference Manual Arm Cortex M4 Devices Generic User Guide Arm Cortex M4 Devices Generic User Guide System memory map...

Page 98: ...bus System bus The system bus is connected to a separate master port on the crossbar Private peripheral PPB bus The PPB provides access to these modules Arm modules such as the NVIC ITM DWT FBP and RO...

Page 99: ...be in one of these states 1 Write Back Write Allocate WBWA 2 Write Through 3 No cache For each defined region there will be 2 bits allocated on the control register see PCCRMR that determines the cac...

Page 100: ...ex M4F Technical Reference Manual Nested Vectored Interrupt Controller System memory map Refer to the MWCT101xS_memory_map xlsx attached to this document Clocking Clock distribution Power management P...

Page 101: ...on IPR register number2 NVIC IPR register number3 Source module 0x0000_0128 74 58 1 14 Low Power Timer 1 Indicates the NVIC s interrupt source number 2 Indicates the NVIC s ISER ICER ISPR ICPR and IAB...

Page 102: ...n Table 7 7 Reference links to related information Topic Related module Reference System memory map Refer to the MWCT101xS_memory_map xlsx attached to Reference Manual for details Clocking Clock distr...

Page 103: ...C_CLKIN Wakeup from alarm interrupt CAN PNET is supported in STOP1 2 modes and will cause wake up Only CAN0 supports PNET feature NMI Non maskable interrupt WDOG 1 Async Interrupt in STOP1 2 Sync Inte...

Page 104: ...Peripheral Bus 7 5 JTAG controller configuration This section summarizes how the module has been configured in the chip Signal multiplexing JTAG controller Figure 7 5 JTAG controller configuration Ta...

Page 105: ..._2003 0x8704_2003 8804_2003 MCM_LMDR2 8424_40A0 8424_40A0 8424_40A0 MCM_PLASC 0007 0007 000F MCM_PLAMC 0007 0007 000F NOTE For WCT101xSF variants SRAM is the tightly coupled SRAM TCM 8 2 Introduction...

Page 106: ...D Register MCM_PID 32 R W 0000_0000h 8 3 5 115 E008_0040 Compute Operation Control Register MCM_CPO 32 R W 0000_0000h 8 3 6 116 E008_0400 Local Memory Descriptor Register MCM_LMDR0 32 R W See section...

Page 107: ...to AXBS input port n is absent 1 A bus slave connection to AXBS input port n is present 8 3 2 Crossbar Switch AXBS Master Configuration MCM_PLAMC PLAMC is a 16 bit read only register identifying the p...

Page 108: ...Field Description 0 A bus master connection to AXBS input port n is absent 1 A bus master connection to AXBS input port n is present Memory map register descriptions MWCT101xS Series Reference Manual...

Page 109: ...RAM arrays Address E008_0000h base Ch offset E008_000Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Reserved SRAMLWP SRAMLAP 0 SRAMUWP SRAMUAP Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 110: ...28 SRAMLAP SRAM_L Arbitration Priority Defines the arbitration scheme and priority for the processor and SRAM backdoor accesses to the SRAM_L array 00 Round robin 01 Special round robin favors SRAM ba...

Page 111: ...onfiguring any other master for example DMA etc as fixed arbitration may generate stalls or underruns on low priority master 0 Fixed priority arbitration 1 Round robin arbitration 8 7 Reserved This fi...

Page 112: ...exceptions and the bus errors associated with the core s cache write buffer The individual event indicators are first qualified with their exception enables and then logically summed to form an inter...

Page 113: ...nable 0 Disable interrupt 1 Enable interrupt 26 FOFCE FPU Overflow Interrupt Enable 0 Disable interrupt 1 Enable interrupt 25 FDZCE FPU Divide by Zero Interrupt Enable 0 Disable interrupt 1 Enable int...

Page 114: ...low has been detected in the processor s FPU After this field is set it remains set until software clears FPSCR UFC 0 No interrupt 1 Interrupt occurred 10 FOFC FPU Overflow Interrupt Status This field...

Page 115: ...he value in this register a bus error occurs See the MPU chapter for more details Address E008_0000h base 30h offset E008_0030h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...

Page 116: ...s read only field is reserved and always has the value 0 2 CPOWOI Compute Operation Wakeup On Interrupt 0 No effect 1 When set the CPOREQ is cleared on any interrupt or exception vector fetch 1 CPOACK...

Page 117: ...ies as well as configurable controls where appropriate Privileged 32 bit reads from a processor core or the debugger return the appropriate processor information Reads from any other bus master return...

Page 118: ...V Reserved Reserved LMSZH LMSZ WY DPW LOCK W Reset x x x x x x x x x x x x x x x x Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R MT Reserved Reserved Reserved CF0 W Reset x x x x x x x x x x x x x x x...

Page 119: ...MEM Size This field provides an encoded value of the local memory size The capacity of the memory is expressed as Size bytes 2 9 LMSZ where LMSZ is non zero a LMSZ 0 indicates the memory is not presen...

Page 120: ...Reserved This field is reserved 7 4 Reserved This field is reserved CF0 Control Field 0 This field is used for TCM ECC control functions CF0 3 Reserved CF0 2 Reserved CF0 1 EERC ECC Enable Read Check...

Page 121: ...ields Privileged writes from other bus masters are ignored Attempted user mode accesses or any access with a size other than 32 bits are terminated with an error Address E008_0000h base 408h offset E0...

Page 122: ...al memories that are not fully populated that is include a memory hole in the upper 25 of the address range this field is used 0 LMEMn is a power of 2 capacity 1 LMEMn is not a power of 2 with a capac...

Page 123: ...g with LMDRn 7 0 this bit locks itself Once locked only reset can clear this bit 0 Writes to the LMDRn 7 0 are allowed 1 Writes to the LMDRn 7 0 are ignored 15 13 MT Memory Type This field defines the...

Page 124: ...enabled 19 17 Reserved This field is reserved This read only field is reserved and always has the value 0 16 Reserved This field is reserved This read only field is reserved and always has the value 0...

Page 125: ...CC Error Location 00 Non correctable ECC event from SRAM_L 01 Non correctable ECC event from SRAM_U 08 1 bit correctable ECC event from SRAM_L 09 1 bit correctable ECC event from SRAM_U 14 PC tag pari...

Page 126: ...4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R EFADD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCM_LMFAR field descriptions Field Description EFADD ECC...

Page 127: ...eld Description 31 OVR Overrun 30 Reserved This field is reserved This read only field is reserved and always has the value 0 29 24 Reserved This field is reserved This read only field is reserved and...

Page 128: ...base 4A0h offset E008_04A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PEFDH W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MC...

Page 129: ...occurs FDZC FPU invalid operation interrupt is enabled FIOCE and an invalid occurs FIOC SRAM_L correctable 1 bit ECC error SRAM_L uncorrectable ECC error SRAM_U correctable 1 bit ECC error SRAM_U unco...

Page 130: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 130 NXP Semiconductors...

Page 131: ...module the number of module instances present in a variant See Figure 2 3 for details on module and instance information 9 2 Introduction The System Integration Module SIM provides system control and...

Page 132: ...Control register CHIPCTL 32 RW 0030_0000h Ch FTM Option Register 0 FTMOPT0 32 RW 0000_0000h 10h LPO Clock Select Register LPOCLKS 32 RW 0000_0003h 18h ADC Options Register ADCOPT 32 RW 0000_0000h 1Ch...

Page 133: ...h Miscellaneous Control register 1 MISCTRL1 32 RW 0000_0000h 9 3 1 2 Chip Control register CHIPCTL 9 3 1 2 1 Offset Register Offset CHIPCTL 4h 9 3 1 2 2 Function SIM_CHIPCTL contains the controls for...

Page 134: ...etained across resets 1b No SRAML retention 20 SRAMU_RETE N SRAMU_RETEN SRAMU retention 0b SRAMU contents are retained across resets 1b No SRAMU retention 19 ADC_SUPPLYE N ADC_SUPPLYEN Enable for inte...

Page 135: ...UT configuration 1 Configure SIM_CHIPCTL CLKOUTSEL 2 Configure SIM_CHIPCTL CLKOUTDIV 3 Enable SIM_CHIPCTL CLKOUTEN While switching CLKOUTEN should be first cleared and then the above sequence should b...

Page 136: ...110b RTC_CLK as selected by SIM_LPOCLKS RTCCLKSEL 1111b For WCT1016S QSPI_2xSFIF_CLK For others Reserved 3 0 ADC_INTERLE AVE_EN ADC interleave channel enable Select ADC interleave pins See section ADC...

Page 137: ...LKSEL FTM2 External Clock Pin Select Selects the external pin used to drive the FTM2 module clock NOTE The selected pin must also be configured for the FTM2 external clock function through the appropr...

Page 138: ...clock driven by TCLK2 pin 11b No clock input 19 18 FTM5CLKSEL FTM5 External Clock Pin Select Selects the external pin used to drive the FTM5 module clock NOTE The selected pin must also be configured...

Page 139: ...onfigured for FTM1 fault function through the appropriate PORT_PCRn field when the fault comes from an external pin TRGMUX_FTM1 SELx corresponds to the FTM1 Fault x input 000b FTM1_FLTx pin 001b TRGMU...

Page 140: ...z clock source for peripherals 00b SOSCDIV1_CLK 01b 32 kHz LPO_CLK 10b 32 kHz RTC_CLKIN clock 11b FIRCDIV1_CLK 3 2 LPOCLKSEL LPO clock source select Selects LPO clock source for peripherals 00b 128 kH...

Page 141: ...0 0 0 0 0 0 0 0 0 0 0 0 9 3 1 5 3 Fields Field Function 31 16 Reserved 15 14 Reserved 13 12 ADC1PRETRG SEL ADC1 pretrigger source select Selects pretrigger source for ADC1 00b PDB pretrigger default 0...

Page 142: ...10b Software pretrigger 11b Reserved 3 1 ADC0SWPRET RG ADC0 software pretrigger sources 000b Software pretrigger disabled 001b Reserved do not use 010b Reserved do not use 011b Reserved do not use 100...

Page 143: ...FTM global load enable This bit is not self clearing For subsequent reload operations it should be cleared and then set 0b FTM Global load mechanism disabled 1b FTM Global load mechanism enabled 14 F...

Page 144: ...hardware triggering 2 FTM2SYNCBIT FTM2 Sync Bit This is used as trigger source for FTM2 See section FTM Hardware Triggers and Synchronization for details on FTM hardware triggering 1 FTM1SYNCBIT FTM1...

Page 145: ...clock is gated 1b QuadSPI internal reference clock is enabled 25 Reserved 24 Reserved 23 FTM7_OBE_CT RL FTM7 OBE CTRL bit 0b The FTM channel output is put to safe state when the FTM counter is enable...

Page 146: ...d FTM_SC PWMENn 1 b1 Otherwise the channel output is tristated 1b The FTM channel output state is retained when the channel is in output mode The output channel is tristated when the channel is in inp...

Page 147: ...TOP2 mode NOTE This bit is reset on POR 0b System clock enabled or STOP2 entry aborted 1b STOP2 entry successful 9 STOP1_MONIT OR STOP1 monitor bit This status bit monitors bus clock status on STOP1 m...

Page 148: ...RAMSIZE RAM size This field specifies the total amount of system RAM available on the chip including FlexRAM 0000b Reserved 0001b Reserved 0010b Reserved 0011b Reserved 0100b Reserved 0101b Reserved 0...

Page 149: ...onding module clock enabled through PCC CGC bit there will not be any transfer error termination This bit field overrides the PCC PR status for the chip 1 Feature is present 0 Feature is not present E...

Page 150: ...k disabled 1b Clock enabled 3 CGCERM ERM Clock Gating Control Controls the clock gating to the ERM 0b Clock disabled 1b Clock enabled 2 CGCDMA DMA Clock Gating Control Controls the clock gating to the...

Page 151: ...havior 9 3 1 10 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Reserved Reserved 0 EEERAMSIZE W Reset u u u u u u u u u u u u u u u u Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DEP...

Page 152: ...See DEPART field description in FTFC chapter 11 2 Reserved 1 Reserved 0 Reserved 9 3 1 11 Unique Identification Register High UIDH 9 3 1 11 1 Offset Register Offset UIDH 54h 9 3 1 11 2 Function NOTE U...

Page 153: ...9 3 1 11 4 Fields Field Function 31 0 UID127_96 Unique Identification Unique identification for the chip 9 3 1 12 Unique Identification Register Mid High UIDMH 9 3 1 12 1 Offset Register Offset UIDMH...

Page 154: ...u 9 3 1 12 4 Fields Field Function 31 0 UID95_64 Unique Identification Unique identification for the chip 9 3 1 13 Unique Identification Register Mid Low UIDML 9 3 1 13 1 Offset Register Offset UIDML...

Page 155: ...u 9 3 1 13 4 Fields Field Function 31 0 UID63_32 Unique Identification Unique identification for the chip 9 3 1 14 Unique Identification Register Low UIDL 9 3 1 14 1 Offset Register Offset UIDL 60h 9...

Page 156: ...D31_0 W Reset u u u u u u u u u u u u u u u u 9 3 1 14 4 Fields Field Function 31 0 UID31_0 Unique Identification Unique identification for the chip 9 3 1 15 System Clock Divider Register 4 CLKDIV4 9...

Page 157: ...the divide value for the fractional clock divider used as a source for trace clock The source clock for the trace clock is set by the SIM_CHIPCTL TRACECLK_SEL Divider output clock Divider input clock...

Page 158: ...0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SW_TR G W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 3 1 16 3 Fields Field Function 31 1 Reserved 0 SW_TRG Software trigger to TRGMUX Writing to this...

Page 159: ...analog or disabled pin muxing mode corresponding to PORT_PCRn MUX 3 b000 Before entering Analog mode ALT0 corresponding to PORT_PCRn MUX 3 b000 for corresponding pads for which Analog functionality i...

Page 160: ...ORT register of PTC3 PTxn the corresponding mapped register is PORTC_PCR3 PORTx_PCRn To find PORTC base address look up the Start address of Port C in Peripheral Memory Map tab in the attached WCT101x...

Page 161: ...te 5 Enable the interrupton the corresponding pin by configuring PORTx_PCRn IRQC 10 1 4 2 Digital input filter configuration sequence while using NMI 1 Configure digital pin filtering controls for the...

Page 162: ...d external interrupt functions Most functions can be configured independently for each pin in the 32 bit port and affect the pin regardless of its pin muxing state There is one instance of the PORT mo...

Page 163: ...g modes 10 3 2 Modes of operation 10 3 2 1 Run mode In Run mode the PORT operates normally 10 3 2 2 Wait mode In Wait mode PORT continues to operate normally and may be configured to exit the Low Powe...

Page 164: ...can assert asynchronously to the system clock Negation may occur at any time and can assert asynchronously to the system clock 10 6 Memory map and register definition Any read or write access to the...

Page 165: ...ORTA_PCR18 32 R W See section 10 6 1 172 4004_904C Pin Control Register n PORTA_PCR19 32 R W See section 10 6 1 172 4004_9050 Pin Control Register n PORTA_PCR20 32 R W See section 10 6 1 172 4004_9054...

Page 166: ...2 R W See section 10 6 1 172 4004_A030 Pin Control Register n PORTB_PCR12 32 R W See section 10 6 1 172 4004_A034 Pin Control Register n PORTB_PCR13 32 R W See section 10 6 1 172 4004_A038 Pin Control...

Page 167: ...Pin Control Register n PORTC_PCR5 32 R W See section 10 6 1 172 4004_B018 Pin Control Register n PORTC_PCR6 32 R W See section 10 6 1 172 4004_B01C Pin Control Register n PORTC_PCR7 32 R W See section...

Page 168: ...Filter Enable Register PORTC_DFER 32 R W 0000_0000h 10 6 7 177 4004_B0C4 Digital Filter Clock Register PORTC_DFCR 32 R W 0000_0000h 10 6 8 178 4004_B0C8 Digital Filter Width Register PORTC_DFWR 32 R...

Page 169: ...See section 10 6 1 172 4004_C07C Pin Control Register n PORTD_PCR31 32 R W See section 10 6 1 172 4004_C080 Global Pin Control Low Register PORTD_GPCLR 32 W always reads 0 0000_0000h 10 6 2 175 4004_C...

Page 170: ...W See section 10 6 1 172 4004_D05C Pin Control Register n PORTE_PCR23 32 R W See section 10 6 1 172 4004_D060 Pin Control Register n PORTE_PCR24 32 R W See section 10 6 1 172 4004_D064 Pin Control Reg...

Page 171: ...ster name Width in bits Access Reset value Section page 4004_D0C8 Digital Filter Width Register PORTE_DFWR 32 R W 0000_0000h 10 6 9 178 Chapter 10 Port Control and Interrupts PORT MWCT101xS Series Ref...

Page 172: ...0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R LK 0 MUX 0 DSE Reserved PFE 0 Reserved PE PS W Reset 0 0 0 0 0 0 0 0 0 Notes MUX field Varies by port See Signal Multiplexing and Sig...

Page 173: ...abled 0001 ISF flag and DMA request on rising edge 0010 ISF flag and DMA request on falling edge 0011 ISF flag and DMA request on either edge 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 10...

Page 174: ...ed on the corresponding pin 1 Passive input filter is enabled on the corresponding pin if the pin is configured as a digital input Refer to the device data sheet for filter characteristics 3 Reserved...

Page 175: ...sters bits 15 0 that are selected by GPWE 10 6 3 Global Pin Control High Register PORTx_GPCHR Only 32 bit writes are supported to this register Address Base address 84h offset Bit 31 30 29 28 27 26 25...

Page 176: ...ol Register is updated with the value in GPWD 10 6 5 Global Interrupt Control High Register PORTx_GICHR Only 32 bit writes are supported to this register Address Base address 8Ch offset Bit 31 30 29 2...

Page 177: ...the completion of the requested DMA transfer Otherwise the flag remains set until a logic 1 is written to the flag If the pin is configured for a level sensitive interrupt and the pin remains asserted...

Page 178: ...served This field is reserved This read only field is reserved and always has the value 0 0 CS Clock Source The digital filter configuration is valid in all digital pin muxing modes Configures the clo...

Page 179: ...n It also includes a flag to indicate that an interrupt has occurred The lower half of the Pin Control register configures the following functions for each pin within the 32 bit port Pullup or pulldow...

Page 180: ...7 2 Global pin control The two global pin control registers allow a single register write to update the lower half of the pin control register on up to 16 pins all with the same value Registers that a...

Page 181: ...transition The PORT module generates a single interrupt that asserts when the interrupt status flag is set for any enabled interrupt for that port The interrupt negates after the interrupt status fla...

Page 182: ...abled digital filters within one port and must be changed only when all digital filters for that port are disabled The output of each digital filter is logic zero after system reset and whenever a dig...

Page 183: ...w to control the ports See Module operation in available power modes for details on available power modes 11 1 2 GPIO ports memory map This chip implements five instances of GPIOs GPIOA to GPIOE The G...

Page 184: ...pin when the pin is configured for any digital function provided the corresponding Port Control and Interrupt module for that pin is enabled Efficient bit manipulation of the general purpose outputs i...

Page 185: ...for the number of GPIO ports available in the device 11 2 3 1 Detailed signal description Table 11 5 GPIO interface detailed signal descriptions Signal I O Description PORTA31 PORTA0 PORTB31 PORTB0 P...

Page 186: ...chip specific Refer to the chip specific GPIO information to see the exact control bits for each port 11 3 1 GPIO register descriptions 11 3 1 1 GPIO Memory map GPIOA base address 400F_F000h GPIOB bas...

Page 187: ...put pin NOTE Do not modify pin configuration registers associated with pins not available in your selected package All unbonded pins not available in your package will default to DISABLE state for low...

Page 188: ...r configures whether to set the fields of the PDOR 11 3 1 3 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W PTSO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7...

Page 189: ...9 8 7 6 5 4 3 2 1 0 R 0 W PTCO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 3 1 4 4 Fields Field Function 31 0 PTCO Port Clear Output Writing to this register updates the contents of the corresponding bi...

Page 190: ...0 W PTTO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 3 1 5 4 Fields Field Function 31 0 PTTO Port Toggle Output Writing to this register updates the contents of the corresponding bit in the PDOR as foll...

Page 191: ...11 10 9 8 7 6 5 4 3 2 1 0 R PDI W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 3 1 6 4 Fields Field Function 31 0 PDI Port Data Input Reads 0 at the unimplemented pins for a particular device Pins that ar...

Page 192: ...on Configures individual port pins for input or output 0b Pin is configured as general purpose input for the GPIO function The pin will be high Z if the port input is disabled in GPIOx_PIDR register 1...

Page 193: ...the port input enable register is set the pin is configured for a digital function and the corresponding Port Control and Interrupt module is enabled The input pin synchronizers are shared with the P...

Page 194: ...output register To facilitate efficient bit manipulation on the general purpose outputs pin data set pin data clear and pin data toggle registers exist to allow one or more outputs within one port to...

Page 195: ...core system bus DMA WCT1015 Arm core code bus Arm core system bus DMA WCT1014 Arm core code bus Arm core system bus DMA 1 Priority in fixed priority mode MCM controls mode selection for global slave...

Page 196: ...information on the layout configuration and programming of the crossbar switch The crossbar switch connects bus masters and bus slaves using a crossbar switch structure This structure allows up to fo...

Page 197: ...t by running an IDLE cycle or by targeting a different slave port for its next access The master can also lose control of the slave port if another higher priority master makes a request to the slave...

Page 198: ...edge to ensure that the proper master if any has control of the slave port The following table describes possible scenarios based on the requesting master port Table 12 3 How the Crossbar Switch gran...

Page 199: ...ster in line is granted access to the slave port at the next transfer boundary or possibly on the next clock cycle if the current master has no pending access request As an example of arbitration in r...

Page 200: ...Initialization application information MWCT101xS Series Reference Manual Rev 3 07 2019 200 NXP Semiconductors...

Page 201: ...rate the Arm Core MPU which would concurrently monitor only core initiated memory accesses In this document the term MPU refers to NXP s system MPU 13 1 1 MPU Slave Port Assignments The memory mapped...

Page 202: ...rocess ID register MCM_PID 13 1 4 Region descriptors and slave port configuration For each chip in the product series the following table shows the numbers of region descriptors and slave ports as wel...

Page 203: ...ation Macro Access Evaluation Macro Mux Address Phase Signals Peripheral Bus MPU_EARn MPU_EDRn Figure 13 1 MPU block diagram The hardware s two dimensional connection matrix is clearly visible with th...

Page 204: ...e assisted maintenance of the descriptor valid bit minimizes coherency issues Alternate programming model view of the access control permissions word Priority given to granting permission over denying...

Page 205: ...ave port 1 EDR1 32 RO 0000_0000h 20h Error Address Register slave port 2 EAR2 32 RO 0000_0000h 24h Error Detail Register slave port 2 EDR2 32 RO 0000_0000h 28h Error Address Register slave port 3 EAR3...

Page 206: ...n Descriptor 7 Word 1 RGD7_WORD1 32 RW 0000_001Fh 478h Region Descriptor 7 Word 2 RGD7_WORD2 32 RW 0000_0000h 47Ch Region Descriptor 7 Word 3 RGD7_WORD3 32 RW 0000_0000h 480h Region Descriptor 8 Word...

Page 207: ...1 RGDAAC1 32 RW 0000_0000h 808h Region Descriptor Alternate Access Control 2 RGDAAC2 32 RW 0000_0000h 80Ch Region Descriptor Alternate Access Control 3 RGDAAC3 32 RW 0000_0000h 810h Region Descriptor...

Page 208: ...write the flag remains set A find first one instruction or equivalent can detect the presence of a captured error 0b No error has occurred for slave port 0 1b An error has occurred for slave port 0 3...

Page 209: ...ed error in EAR4 and EDR4 This bit is set when the hardware detects an error and records the faulting address and attributes It is cleared by writing one to it If another error is captured at the exac...

Page 210: ...ng access is captured in the corresponding EDRn at the same time This register and the corresponding EDRn contain the most recent access error there are no hardware interlocks with CESR SPERRn as the...

Page 211: ...ts of error detail are captured in this read only register and the corresponding bit in CESR SPERRn is set Information on the faulting address is captured in the corresponding EARn register at the sam...

Page 212: ...n error was caused by an overlapping set of region descriptors 15 8 EPID Error Process Identification Records the process identifier of the faulting reference The process identifier is typically drive...

Page 213: ...bit RGDn_WORD3 VLD 13 4 5 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R SRTADDR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SRTADDR 0 W Res...

Page 214: ...its 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R ENDADDR W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ENDADDR Reserved W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1...

Page 215: ...rs 4 7 are limited to separate read and write permissions For the privilege rights of bus masters 0 3 there are three flags associated with this function Read r refers to accessing the referenced memo...

Page 216: ...lowed 28 M6WE Bus Master 6 Write Enable 0b Bus master 6 writes terminate with an access error and the write is not performed 1b Bus master 6 writes allowed 27 M5RE Bus Master 5 Read Enable 0b Bus mast...

Page 217: ...controls execute permissions For each bit 0b An attempted access of that mode may be terminated with an access error if not allowed by another descriptor and the access not performed 1b Allows the gi...

Page 218: ...ermissions For each bit 0b An attempted access of that mode may be terminated with an access error if not allowed by another descriptor and the access not performed 1b Allows the given access type to...

Page 219: ...RGDn_WORD2 MxPE is set For more information on the handling of the PID and PIDMASK see Access Evaluation Hit Determination 15 1 Reserved 0 VLD Valid Signals the region descriptor is valid Any write t...

Page 220: ...4 Fields Field Function 31 5 ENDADDR End Address Defines the most significant bits of the 31 modulo 32 byte end address of the memory region NOTE The MPU does not verify that ENDADDR SRTADDR 4 0 Reser...

Page 221: ...address using an operand data fetch Write w refers to updating the referenced memory address using a store data instruction Execute x refers to reading the referenced memory address using an instruct...

Page 222: ...rminate with an access error and the write is not performed 1b Bus master 4 writes allowed 23 Reserved This bit must be written with a zero 22 21 M3SM Bus Master 3 Supervisor Mode Access Control Defin...

Page 223: ...d r write w and execute x permissions In M1UM 2 0 M1UM 2 controls read permissions M1UM 1 controls write permissions and M1UM 0 controls execute permissions For each bit 0b An attempted access of that...

Page 224: ...0 R 0 VLD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 4 11 4 Fields Field Function 31 24 PID Process Identifier Specifies the process identifier that is included in the region hit determination if RGDn...

Page 225: ...or is invalid 1b Region descriptor is valid 13 4 12 Region Descriptor Alternate Access Control 0 RGDA AC0 13 4 12 1 Offset Register Offset RGDAAC0 800h 13 4 12 2 Function Because software may adjust o...

Page 226: ...rror and the read is not performed 1b Bus master 6 reads allowed 28 M6WE Bus Master 6 Write Enable 0b Bus master 6 writes terminate with an access error and the write is not performed 1b Bus master 6...

Page 227: ...UM 2 0 M2UM 2 controls read permissions M2UM 1 controls write permissions and M2UM 0 controls execute permissions For each bit 0b An attempted access of that mode may be terminated with an access erro...

Page 228: ...bits enabling read r write w and execute x permissions In M0UM 2 0 M0UM 2 controls read permissions M0UM 1 controls write permissions and M0UM 0 controls execute permissions For each bit 0b An attemp...

Page 229: ...nd the read is not performed 1b Bus master 6 reads allowed 28 M6WE Bus Master 6 Write Enable 0b Bus master 6 writes terminate with an access error and the write is not performed 1b Bus master 6 writes...

Page 230: ...In M2UM 2 0 M2UM 2 controls read permissions M2UM 1 controls write permissions and M2UM 0 controls execute permissions For each bit 0b An attempted access of that mode may be terminated with an acces...

Page 231: ...0 controls execute permissions For each bit 0b An attempted access of that mode may be terminated with an access error if not allowed by another descriptor and the access not performed 1b Allows the g...

Page 232: ...D is the valid bit NOTE The MPU does not verify that ENDADDR SRTADDR In addition to the comparison of the reference address versus the region descriptor s start and end addresses the optional process...

Page 233: ...r and error terminations For each slave port monitored the MPU performs a reduction AND of all the individual terms from each access evaluation macro This expression then terminates the bus cycle with...

Page 234: ...ing a new memory region Load the appropriate region descriptor into an available RGDn using four sequential 32 bit writes The hardware assists in the maintenance of the valid bit so if this approach i...

Page 235: ...OR operator The following dual core system example contains four bus masters The two processors CP0 CP1 Two DMA engines DMA1 a traditional data movement engine transferring data between RAM and perip...

Page 236: ...r passing data from CP1 to CP0 For this overlapping space CP0 has r r permission while CP1 has rw r rw permission The non overlapped space of RGD4 defines a private data and stack area for CP1 only Th...

Page 237: ...eripherals with corresponding AIPS Peripheral bridge slot numbers from 0 31 AIPS_OPACR0 OPACR95 refer to off platform peripherals with corresponding AIPS Peripheral bridge slot numbers from 32 127 For...

Page 238: ...ripherals on this chip The peripheral bridge occupies 64 MB of the address space which is divided into peripheral slots of 4 KB It might be possible that all the peripheral slots are not used See the...

Page 239: ...PACRD 32 RW 4400_0000h 40h Off Platform Peripheral Access Control Register OPACRA 32 RW 4400_4444h 44h Off Platform Peripheral Access Control Register OPACRB 32 RW 0004_4440h 48h Off Platform Peripher...

Page 240: ...fic AIPS information 14 3 1 2 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 MTR0 MTW0 MPL0 0 MTR1 MTW1 MPL1 0 MTR2 MTW2 MPL2 0 MTR3 MTW3 MPL3 W Reset 0 0 1 0 1 1 0 0 0 0 1 1 0 1 1...

Page 241: ...aster are forced to user mode 1b Accesses from this master are not forced to user mode 23 Reserved 22 MTR2 Master 2 Trusted For Read Determines whether the master is trusted for read accesses 0b This...

Page 242: ...6 4 Reserved 3 Reserved 2 0 Reserved 14 3 1 3 Peripheral Access Control Register PACRA 14 3 1 3 1 Offset Register Offset PACRA 20h 14 3 1 3 2 Function Each PACR register consists of eight 4 bit PACR f...

Page 243: ...This peripheral does not require supervisor privilege level for accesses 1b This peripheral requires supervisor privilege level for accesses 29 WP0 Write Protect Determines whether the peripheral allo...

Page 244: ...s attempted access terminates with an error response and no peripheral access initiates 0b This peripheral allows write accesses 1b This peripheral is write protected 24 TP1 Trusted Protect Determines...

Page 245: ...s set the master privilege level must indicate the supervisor access attribute and the MPRx MPLn control field for the master must be set If not access terminates with an error response and no periphe...

Page 246: ...master are allowed 1b Accesses from an untrusted master are not allowed 23 20 Reserved 19 16 Reserved 15 12 Reserved 11 Reserved 10 SP5 Supervisor Protect Determines whether the peripheral requires su...

Page 247: ...he memory map slot of the peripheral See the chip specific AIPS information for the field assignment of a particular peripheral Every PACR field to which no peripheral is assigned is reserved Reads to...

Page 248: ...ted master are not allowed 27 Reserved 26 SP1 Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses When this field is set the master privilege level mu...

Page 249: ...ach OPACR field is defined by the memory map slot of the peripheral See the chip specific AIPS information for the field assignment of a particular peripheral 14 3 1 6 3 Diagram Bits 31 30 29 28 27 26...

Page 250: ...sted master are not allowed 27 Reserved 26 SP1 Supervisor Protect Determines whether the peripheral requires supervisor privilege level for access When this field is set the master privilege level mus...

Page 251: ...e MPRx MPLn control field for the master must be set If not access terminates with an error response and no peripheral access initiates 0b This peripheral does not require supervisor privilege level f...

Page 252: ...set If not access terminates with an error response and no peripheral access initiates 0b This peripheral does not require supervisor privilege level for accesses 1b This peripheral requires supervis...

Page 253: ...Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses When this field is set the master privilege level must indicate the supervisor access attribute an...

Page 254: ...ed by an untrusted master the access terminates with an error response and no peripheral access initiates 0b Accesses from an untrusted master are allowed 1b Accesses from an untrusted master are not...

Page 255: ...eripheral is write protected 4 TP6 Trusted Protect Determines whether the peripheral allows accesses from an untrusted master When this field is set and an access is attempted by an untrusted master t...

Page 256: ...set and a write access is attempted access terminates with an error response and no peripheral access initiates 0b This peripheral allows write accesses 1b This peripheral is write protected 24 TP1 Tr...

Page 257: ...does not require supervisor privilege level for accesses 1b This peripheral requires supervisor privilege level for accesses 5 WP6 Write Protect Determines whether the peripheral allows write accesse...

Page 258: ...e allowed 1b Accesses from an untrusted master are not allowed 14 3 1 9 Off Platform Peripheral Access Control Register OPACRD 14 3 1 9 1 Offset Register Offset OPACRD 4Ch 14 3 1 9 2 Function Each OPA...

Page 259: ...ed master are not allowed 27 Reserved 26 SP1 Supervisor Protect Determines whether the peripheral requires supervisor privilege level for access When this field is set the master privilege level must...

Page 260: ...ol field for the master must be set If not access terminates with an error response and no peripheral access initiates 0b This peripheral does not require supervisor privilege level for accesses 1b Th...

Page 261: ...ripheral access initiates 0b Accesses from an untrusted master are allowed 1b Accesses from an untrusted master are not allowed 7 4 Reserved 3 0 Reserved 14 3 1 10 Off Platform Peripheral Access Contr...

Page 262: ...This peripheral requires supervisor privilege level for accesses 29 WP0 Write Protect Determines whether the peripheral allows write accesses When this field is set and a write access is attempted acc...

Page 263: ...is peripheral is write protected 4 TP6 Trusted Protect Determines whether the peripheral allows accesses from an untrusted master When this field is set and an access is attempted by an untrusted mast...

Page 264: ...ccess terminates with an error response and no peripheral access initiates 0b This peripheral allows write accesses 1b This peripheral is write protected 28 TP0 Trusted Protect Determines whether the...

Page 265: ...ccesses 1b This peripheral is write protected 20 TP2 Trusted Protect Determines whether the peripheral allows accesses from an untrusted master When this bit is set and an access is attempted by an un...

Page 266: ...s from an untrusted master are allowed 1b Accesses from an untrusted master are not allowed 11 Reserved 10 SP5 Supervisor Protect Determines whether the peripheral requires supervisor privilege level...

Page 267: ...chip specific AIPS information for the field assignment of a particular peripheral 14 3 1 12 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 SP2 WP2 TP2 0 W Reset 0 0 0 0 0 0 0...

Page 268: ...Rx MPLn control bit for the master must be set If not access terminates with an error response and no peripheral access initiates 0b This peripheral does not require supervisor privilege level for acc...

Page 269: ...ripheral access initiates 0b Accesses from an untrusted master are allowed 1b Accesses from an untrusted master are not allowed 7 4 Reserved 3 0 Reserved 14 3 1 13 Off Platform Peripheral Access Contr...

Page 270: ...evel for accesses 1b This peripheral requires supervisor privilege level for accesses 21 WP2 Write Protect Determines whether the peripheral allows write accesses When this field is set and a write ac...

Page 271: ...ot of the peripheral See the chip specific AIPS information for the field assignment of a particular peripheral 14 3 1 14 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 SP1 WP1 T...

Page 272: ...are not allowed 23 20 Reserved 19 Reserved 18 SP3 Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses When this field is set the master privilege lev...

Page 273: ...ield for the master must be set If not access terminates with an error response and no peripheral access initiates 0b This peripheral does not require supervisor privilege level for accesses 1b This p...

Page 274: ...access terminates with an error response and no peripheral access initiates 0b This peripheral does not require supervisor privilege level for accesses 1b This peripheral requires supervisor privileg...

Page 275: ...Protect Determines whether the peripheral requires supervisor privilege level for access When this bit is set the master privilege level must indicate the supervisor access attribute and the MPRx MPL...

Page 276: ...sted master the access terminates with an error response and no peripheral access initiates 0b Accesses from an untrusted master are allowed 1b Accesses from an untrusted master are not allowed 15 Res...

Page 277: ...rved 2 SP7 Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses When this field is set the master privilege level must indicate the supervisor access a...

Page 278: ...SP0 Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses When this field is set the master privilege level must indicate the supervisor access attribut...

Page 279: ...and an access is attempted by an untrusted master the access terminates with an error response and no peripheral access initiates 0b Accesses from an untrusted master are allowed 1b Accesses from an u...

Page 280: ...ether the peripheral allows write accesses When this field is set and a write access is attempted access terminates with an error response and no peripheral access initiates 0b This peripheral allows...

Page 281: ...bute and the MPRx MPLn control field for the master must be set If not access terminates with an error response and no peripheral access initiates 0b This peripheral does not require supervisor privil...

Page 282: ...re allowed 1b Accesses from an untrusted master are not allowed 7 Reserved 6 SP6 Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses When this field i...

Page 283: ...the access terminates with an error response and no peripheral access initiates 0b Accesses from an untrusted master are allowed 1b Accesses from an untrusted master are not allowed 14 4 Functional de...

Page 284: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 284 NXP Semiconductors...

Page 285: ...GMUX module can trigger a DMA transfer on the first four DMA channels for example the LPIT can trigger DMA via TRGMUX See Figure 17 2 for module interconnectivity details The LPIT DMA periodic trigger...

Page 286: ...Trigger 1 Trigger z DMA channel 1 DMAMUX Figure 15 1 DMAMUX block diagram 15 2 2 Features The DMAMUX module provides these features Up to 61 peripheral slots and up to 2 always on slots can be routed...

Page 287: ...A channel The operation of the DMAMUX in this mode is completely transparent to the system Periodic Trigger mode In this mode a DMA source may only request a DMA transfer such as when a transmit buffe...

Page 288: ...ociated with one of the DMA slots peripheral slots or always on slots in the system NOTE Setting multiple CHCFG registers with the same source value will result in unpredictable behavior This is true...

Page 289: ...al description The primary purpose of the DMAMUX is to provide flexibility in the system s use of the available DMA channels As such configuration of the DMAMUX is intended to be a static procedure do...

Page 290: ...fer cannot be guaranteed DMA channel 0 Source 1 Source 2 Source 3 Always 1 DMA channel m 1 Always y Trigger m Source x Trigger 1 Figure 15 2 DMAMUX triggered channels The DMA channel triggering capabi...

Page 291: ...with a trigger as described above After it has been set up the SPI will request DMA transfers presumably from memory as long as its transmit buffer is empty By using a trigger on this channel the SPI...

Page 292: ...ernal bus or vice versa Similar to memory to memory transfers this is typically done as quickly as possible Any DMA transfer that requires software activation Any DMA transfer that should be explicitl...

Page 293: ...5 5 Initialization application information This section provides instructions for initializing the DMA channel MUX 15 5 1 Reset The reset state of each individual bit is shown in Memory map register d...

Page 294: ...CHCFG ENBL and CHCFG TRIG fields of the DMA channel 3 Ensure that the DMA channel is properly configured in the DMA The DMA channel may be enabled at this point 4 Select the source to be routed to the...

Page 295: ...nto any of the CHCFG registers Additionally some module specific configuration may be necessary See the appropriate section for more details To switch the source of a DMA channel 1 Disable the DMA cha...

Page 296: ..._ADDR 0x0009 volatile unsigned char CHCFG10 volatile unsigned char DMAMUX_BASE_ADDR 0x000A volatile unsigned char CHCFG11 volatile unsigned char DMAMUX_BASE_ADDR 0x000B volatile unsigned char CHCFG12...

Page 297: ...Chips Number of channels WCT1014S 16 WCT1015S 16 WCT1016S 16 16 2 Introduction The enhanced direct memory access eDMA controller is a second generation module capable of performing complex data trans...

Page 298: ...lock parts The eDMA module is partitioned into two major modules the eDMA engine and the transfer control descriptor local memory The eDMA engine is further partitioned into four submodules Table 16 2...

Page 299: ...bitration This block implements the first section of the eDMA programming model as well as the channel arbitration logic The programming model registers are connected to the internal peripheral bus Th...

Page 300: ...count An outer data transfer loop defined by a major iteration count Channel activation via one of three methods Explicit software initiation Initiation via a channel to channel linking mechanism for...

Page 301: ...is set the eDMA stops transferring data If Debug mode is entered while a channel is active the eDMA continues operation until the channel retires Wait Before entering Wait mode the DMA attempts to com...

Page 302: ...F DLAST_SGA BITER E_LINK BITER or BITER LINKCH BITER START INT_MAJ INT_HALF D_REQ E_SG MAJOR E_LINK ACTIVE DONE BWC MAJOR LINKCH NBYTES 0000h 0004h 0008h DMA_CR EMLM enabled 000Ch 0010h 0014h 0018h 00...

Page 303: ...hannel Priority Register DCHPRI1 8 RW 01h 103h Channel Priority Register DCHPRI0 8 RW 00h 104h Channel Priority Register DCHPRI7 8 RW 07h 105h Channel Priority Register DCHPRI6 8 RW 06h 106h Channel P...

Page 304: ...s Adjustment Scatter Gather Address TCD0_DLASTSGA TCD15_DLASTSGA 32 RW Table 16 4 101Ch 11FCh TCD Control and Status TCD0_CSR TCD15_CSR 16 RW Table 16 4 101Eh 11FEh TCD Beginning Minor Loop Link Major...

Page 305: ...inor loop offset should be applied to the source address TCDn_SADDR upon minor loop completion a destination enable bit DMLOE to specify the minor loop offset should be applied to the destination addr...

Page 306: ...llow the minor loop offset to be applied to the source address the destination address or both The NBYTES field is reduced when either offset is enabled 6 CLM Continuous Link Mode NOTE Do not use cont...

Page 307: ...3 Error Status Register ES 16 4 5 3 1 Offset Register Offset ES 4h 16 4 5 3 2 Function The ES provides information concerning the last recorded channel error Channel errors can be caused by A configu...

Page 308: ...error was a configuration error in the channel priorities Channel priorities are not unique 13 12 Reserved 11 8 ERRCHN Error Channel Number or Canceled Channel Number The channel number of the last r...

Page 309: ...nabled TCDn_DLASTSGA is not on a 32 byte boundary 1 SBE Source Bus Error 0b No source bus error 1b The last recorded error was a bus error on a source read 0 DBE Destination Bus Error 0b No destinatio...

Page 310: ...channel is disabled 1b The DMA request signal for the corresponding channel is enabled 12 ERQ12 Enable DMA Request 12 0b The DMA request signal for the corresponding channel is disabled 1b The DMA re...

Page 311: ...esponding channel is disabled 1b The DMA request signal for the corresponding channel is enabled 1 ERQ1 Enable DMA Request 1 0b The DMA request signal for the corresponding channel is disabled 1b The...

Page 312: ...or corresponding channel generates an error interrupt request 12 EEI12 Enable Error Interrupt 12 0b The error signal for corresponding channel does not generate an error interrupt 1b The assertion of...

Page 313: ...r signal for corresponding channel generates an error interrupt request 1 EEI1 Enable Error Interrupt 1 0b The error signal for corresponding channel does not generate an error interrupt 1b The assert...

Page 314: ...CEEI Clear Enable Error Interrupt Clears the corresponding bit in EEI 16 4 5 7 Set Enable Error Interrupt Register SEEI 16 4 5 7 1 Offset Register Offset SEEI 19h 16 4 5 7 2 Function The SEEI provides...

Page 315: ...5 4 3 2 1 0 R 0 0 0 W NOP SAE E 0 SE EI Reset 0 0 0 0 0 0 0 0 16 4 5 7 4 Fields Field Function 7 NOP No Op enable 0b Normal operation 1b No operation ignore the other bits in this register 6 SAEE Sets...

Page 316: ...other three bytes of the word would all have their NOP bit set so that that these register will not be affected by the write Reads of this register return all zeroes NOTE Disable a channel s hardware...

Page 317: ...ile not affecting the other registers addressed in the write In such a case the other three bytes of the word would all have their NOP bit set so that that these register will not be affected by the w...

Page 318: ...ing all DONE bits to be cleared If the NOP bit is set the command is ignored This allows you to set a single byte wide register with a 32 bit write while not affecting the other registers addressed in...

Page 319: ...write causes the START bit in the corresponding transfer control descriptor to be set Setting the SAST bit provides a global set function forcing all START bits to be set If the NOP bit is set the com...

Page 320: ...le memory mapped mechanism to clear a given bit in the ERR to disable the error condition flag for a given channel The given value on a register write causes the corresponding bit in the ERR to be cle...

Page 321: ...request for a given channel The given value on a register write causes the corresponding bit in the INT to be cleared Setting the CAIR bit provides a global clear function forcing the entire contents...

Page 322: ...ction The INT register provides a bit map for the 16 channels signaling the presence of an interrupt request for each channel Depending on the appropriate bit setting in the transfer control descripto...

Page 323: ...Function 31 16 Reserved 15 INT15 Interrupt Request 15 0b The interrupt request for corresponding channel is cleared 1b The interrupt request for corresponding channel is active 14 INT14 Interrupt Req...

Page 324: ...esponding channel is active 3 INT3 Interrupt Request 3 0b The interrupt request for corresponding channel is cleared 1b The interrupt request for corresponding channel is active 2 INT2 Interrupt Reque...

Page 325: ...t position clears the corresponding channel s error status A zero in any bit position has no affect on the corresponding channel s current error status The CERR is provided so the error indicator for...

Page 326: ...n this channel has occurred 6 ERR6 Error In Channel 6 0b An error in this channel has not occurred 1b An error in this channel has occurred 5 ERR5 Error In Channel 5 0b An error in this channel has no...

Page 327: ...4 5 16 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R HRS15 HRS14 HRS13 HRS12 HRS11 HRS10 HRS...

Page 328: ...are service request for channel 11 is not present 1b A hardware service request for channel 11 is present 10 HRS10 Hardware Request Status Channel 10 The HRS bit for its respective channel remains ass...

Page 329: ...he Request is completed and Channel is free the HRS bit is automatically cleared by hardware 0b A hardware service request for channel 3 is not present 1b A hardware service request for channel 3 is p...

Page 330: ...0b Disable asynchronous DMA request for channel 15 1b Enable asynchronous DMA request for channel 15 14 EDREQ_14 Enable asynchronous DMA request in stop mode for channel 14 0b Disable asynchronous DM...

Page 331: ...ous DMA request for channel 5 1b Enable asynchronous DMA request for channel 5 4 EDREQ_4 Enable asynchronous DMA request in stop mode for channel 4 0b Disable asynchronous DMA request for channel 4 1b...

Page 332: ...meric value for example 0 is the lowest priority 1 is the next higher priority then 2 3 etc Software must program the channel priorities with unique values otherwise a configuration error is reported...

Page 333: ...pended by the service request of a higher priority channel 6 DPA Disable Preempt Ability This field resets to 0 0b Channel n can suspend a lower priority channel 1b Channel n cannot suspend any channe...

Page 334: ...u u u u u u u u u u 16 4 5 19 4 Fields Field Function 31 0 SADDR Source Address Memory address pointing to the source data 16 4 5 20 TCD Signed Source Address Offset TCD0_SOFF TCD15_ SOFF 16 4 5 20 1...

Page 335: ...performed on the original register value Setting this field provides the ability to implement a circular data queue easily For data queues requiring power of 2 size bytes the queue should start at a 0...

Page 336: ...Register Offset TCDn_NBYTES_MLNO 1008h n 20h 16 4 5 22 2 Function This register or one of the next two registers TCD_NBYTES_MLOFFNO TCD_NBYTES_MLOFFYES defines the number of bytes to transfer per req...

Page 337: ...operation and cannot be halted It can however be stalled by using the bandwidth control field or via preemption After the minor count is exhausted the SADDR and DADDR values are written back into the...

Page 338: ...TE S W Reset u u u u u u u u u u u u u u u u Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R NBYTES W Reset u u u u u u u u u u u u u u u u 16 4 5 23 4 Fields Field Function 31 SMLOE Source Minor Loop Of...

Page 339: ...NBYTES_MLOFFYES TCD15_NB YTES_MLOFFYES 16 4 5 24 1 Offset For n 0 to 15 Register Offset TCDn_NBYTES_MLOFF YES 1008h n 20h 16 4 5 24 2 Function One of three registers this register TCD_NBYTES_MLNO or T...

Page 340: ...presents a sign extended offset applied to the source or destination address to form the next state value after the minor loop completes 9 0 NBYTES Minor Byte Transfer Count Number of bytes to be tran...

Page 341: ...ompletion of the major iteration count This value can be applied to restore the source address to the initial value or adjust the address to reference the next data structure This register uses two s...

Page 342: ...unction 31 0 DADDR Destination Address Memory address pointing to the destination data 16 4 5 27 TCD Signed Destination Address Offset TCD0_DOFF TCD15_DOFF 16 4 5 27 1 Offset For n 0 to 15 Register Of...

Page 343: ...uration and the channel s current iteration count It is the same register as TCD Current Minor Loop Link Major Loop Count Channel Linking Enabled TCD0_CITER_ELINKYES TCD15_CITER_ ELINKYES but its fiel...

Page 344: ...s for example final source and destination address calculations optionally generating an interrupt to signal channel completion before reloading the CITER field from the Beginning Iteration Count BITE...

Page 345: ...is enabled ELINK 1 then after the minor loop is exhausted the eDMA engine initiates a channel service request to the channel defined by this field by setting that channel s TCDn_CSR START bit 8 0 CIT...

Page 346: ...on address at the completion of the major iteration count This value can apply to restore the destination address to the initial value or adjust the address to reference the next data structure This f...

Page 347: ...destination sizes are equal this field is ignored between the first and second transfers and after the last write of each minor loop This behavior is a side effect of reducing start up latency 00b No...

Page 348: ...er gather format The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution 3 DREQ Disable Request If this flag is set the...

Page 349: ...link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR START bit of the specified channel If channel linking is disabled the BITER value extends to 15...

Page 350: ...te a single service request the initial values of BITER and CITER should be 0x0001 16 4 5 33 TCD Beginning Minor Loop Link Major Loop Count Channel Linking Enabled TCD0_BITER_ELINKYES TCD1 5_BITER_ELI...

Page 351: ...he software loads the TCD this field must be set equal to the corresponding CITER field otherwise a configuration error is reported As the major iteration count is exhausted the contents of this field...

Page 352: ...gh the control module then into the program model and channel arbitration In the next cycle the channel arbitration performs using the fixed priority or round robin algorithm After arbitration is comp...

Page 353: ...ssing continues until the minor byte count has transferred After the minor byte count has moved the final phase of the basic data flow is performed In this segment the address path logic performs the...

Page 354: ...l setting in the transfer control descriptor or an illegal priority register setting in Fixed Arbitration mode or An error termination to a bus master read or write cycle A configuration error is repo...

Page 355: ...if the scatter gather address DLAST_SGA is not aligned on a 32 byte boundary If minor loop channel linking is enabled upon channel completion a configuration error is reported when the link is attemp...

Page 356: ...ta transfer in the event the full data transfer is no longer needed The cancel transfer bit does not abort the channel It simply stops the transferring of data and then retires the channel through its...

Page 357: ...en a channel s preempt ability is disabled that channel cannot suspend a lower priority channel s data transfer regardless of the lower priority channel s ECP setting This allows for a pool of low pri...

Page 358: ...op channel linking and scatter gather operations if enabled Table 16 5 TCD Control and Status fields TCDn_CSR field name Description START Control bit to start channel explicitly when using a software...

Page 359: ...bytes added to current address after each transfer often the same value as xSIZE Each DMA source S and destination D has its own Address xADDR Size xSIZE Offset xOFF Modulo xMOD Last Address Adjustmen...

Page 360: ...considerations for the eDMA 16 6 3 1 Fixed channel arbitration In this mode the channel service request from the highest priority channel is selected to execute 16 6 3 2 Round robin channel arbitratio...

Page 361: ...o the TCDn_CSR START bit requests channel service 2 The channel is selected by arbitration for servicing 3 eDMA engine writes TCDn_CSR DONE 0 TCDn_CSR START 0 TCDn_CSR ACTIVE 1 4 eDMA engine reads cha...

Page 362: ...Dn_SLAST 32 TCDn_DLAST_SGA 32 This would generate the following sequence of events 1 First hardware that is eDMA peripheral request for channel service 2 The channel is selected by arbitration for ser...

Page 363: ...transfers are executed as follows a Read byte from location 0x1010 read byte from location 0x1011 read byte from 0x1012 read byte from 0x1013 b Write 32 bits to location 0x2010 first iteration of the...

Page 364: ...e a circular buffer is created where the address wraps to the original value while the 28 upper address bits 0x1234567x retain their original value In this example the source address is set to 0x12345...

Page 365: ...er s model The TCD status bits execute the following sequence for a hardware activated channel Stage TCDn_CSR bits State START ACTIVE DONE 1 0 0 0 Channel service request via hardware peripheral reque...

Page 366: ...set simultaneously in the global TCD map a higher priority channel is actively preempting a lower priority channel 16 6 6 Channel Linking Channel linking or chaining is a mechanism where one channel s...

Page 367: ...ng table summarizes how a DMA channel can link to another DMA channel i e use another channel s TCD at the end of a loop Table 16 7 Channel Linking Parameters Desired Link Behavior TCD Control Field N...

Page 368: ...ELINK would be set in the programmer s model but it would be unclear whether the actual link was made before the channel retired The following coherency model is recommended when executing a dynamic c...

Page 369: ...ding the MAJORLINKCH field and the ESG bit with a single read For both dynamic channel linking and scatter gather requests the TCD local memory controller forces the TCD MAJOR E_LINK and E_SG bits to...

Page 370: ...using major loop channel linking For a channel using major loop channel linking the coherency model described here may be used for a dynamic scatter gather request This method uses the TCD DLAST_SGA...

Page 371: ...MA channel 1 Stop the DMA service request at the peripheral first Confirm it has been disabled by reading back the appropriate register in the peripheral 2 Check the DMA s Hardware Request Status Regi...

Page 372: ...channel If no service request is present disable the DMA channel by clearing the channel s ERQ bit If a service request is present wait until the request has been processed and the HRS bit reads zero...

Page 373: ...d Figure 17 3 for available input triggers With the TRGMUX each peripheral that accepts external triggers usually has one specific 32 bit trigger control register Each control register supports up to...

Page 374: ...Modules that need more than four trigger inputs such as for external output have multiple control registers The following figures show the superset of trigger inputs outputs and control registers for...

Page 375: ..._PULSE_OUT in36 out36 PDB1_CH0_TRIG in37 out37 X out38 X PDB1_PULSE_OUT in39 out39 X out40 FTM0_HWTRIG0 TRGMUX_FTM0 out41 FTM0_FAULT0 out42 FTM0_FAULT1 RTC_alarm in43 out43 FTM0_FAULT2 RTC_second in44...

Page 376: ...in23 out87 X FTM1_INIT_TRIG in24 out88 FTM1_EXT_TRIG in25 out89 X FTM2_INIT_TRIG in26 out90 X FTM2_EXT_TRIG in27 out91 X FTM3_INIT_TRIG in28 TRGMUX_LPSPI0 out92 LPSPI0_TRG FTM3_EXT_TRIG in29 out93 X...

Page 377: ...registers are present only on some WCT101xS products The following table lists registers that vary by product Table 17 1 Chip specific TRGMUX registers Register WCT1014S WCT1015S WCT1016S TRGMUX_LPI2...

Page 378: ...rigger for output 0 SEL1 selects the trigger for output 1 SEL2 selects the trigger for output 2 SEL3 selects the trigger for output 3 output x Figure 17 4 TRGMUX block diagram Each peripheral has its...

Page 379: ...LPIT_CH0 0001_0010 0x12 LPIT_CH1 0001_0011 0x13 LPIT_CH2 0001_0100 0x14 LPIT_CH3 0001_0101 0x15 LPTMR0 0001_0110 0x16 FTM0_INIT_TRIG 0001_0111 0x17 FTM0_EXT_TRIG 0001_1000 0x18 FTM1_INIT_TRIG 0001_10...

Page 380: ...0011_0111 0x37 LPI2C0_Master_trigger 0011_1000 0x38 LPI2C0_Slave_trigger 0011_1001 0x39 Reserved 0011_1010 0x3A Reserved 0011_1011 0x3B LPSPI0_Frame 0011_1100 0x3C LPSPI0_RX_data 0011_1101 0x3D LPSPI1...

Page 381: ...0101_1100 0x5C Reserved 0101_1101 0x5D Reserved 0101_1110 0x5E Reserved 0101_1111 0x5F Reserved 0110_0000 0x60 Reserved 0110_0001 0x61 Reserved 0110_0010 0x62 Reserved 0110_0011 0x63 Reserved 0110_010...

Page 382: ...TRGMUX ADC1 Register ADC1 32 RW 0000_0000h 1Ch TRGMUX CMP0 Register CMP0 32 RW 0000_0000h 28h TRGMUX FTM0 Register FTM0 32 RW 0000_0000h 2Ch TRGMUX FTM1 Register FTM1 32 RW 0000_0000h 30h TRGMUX FTM2...

Page 383: ...AMUX0 Register DMAMUX0 17 4 1 2 1 Offset Register Offset DMAMUX0 0h 17 4 1 2 2 Function This register is for the DMAMUX0 module 17 4 1 2 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 384: ...t for peripheral trigger input 2 For the field setting definitions see Memory map and register definition 15 This read only bit field is reserved and always has the value 0 14 8 SEL1 Trigger MUX Input...

Page 385: ...Memory map and register definition 23 This read only bit field is reserved and always has the value 0 22 16 SEL2 Trigger MUX Input 2 Source Select This read write bit field is used to configure the M...

Page 386: ...s TRGMUX register cannot be changed until the next system reset clears LK 0b Register can be written 1b Register cannot be written until the next system Reset 30 24 SEL3 Trigger MUX Input 3 Source Sel...

Page 387: ...t field is used to configure the MUX select for peripheral trigger input 0 For the field setting definitions see Memory map and register definition 17 4 1 5 TRGMUX ADC0 Register ADC0 17 4 1 5 1 Offset...

Page 388: ...d to configure the MUX select for peripheral trigger input 2 For the field setting definitions see Memory map and register definition 15 This read only bit field is reserved and always has the value 0...

Page 389: ...Memory map and register definition 23 This read only bit field is reserved and always has the value 0 22 16 SEL2 Trigger MUX Input 2 Source Select This read write bit field is used to configure the M...

Page 390: ...ot The LK bit can only be written once after any system reset Once LK is set the SELx bits in this TRGMUX register cannot be changed until the next system reset clears LK 0b Register can be written 1b...

Page 391: ...4 1 8 TRGMUX FTM0 Register FTM0 17 4 1 8 1 Offset Register Offset FTM0 28h 17 4 1 8 2 Function This register is for the FTM0 module 17 4 1 8 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 392: ...select for peripheral trigger input 2 For the field setting definitions see Memory map and register definition 15 This read only bit field is reserved and always has the value 0 14 8 SEL1 Trigger MUX...

Page 393: ...Memory map and register definition 23 This read only bit field is reserved and always has the value 0 22 16 SEL2 Trigger MUX Input 2 Source Select This read write bit field is used to configure the M...

Page 394: ...RGMUX register cannot be changed until the next system reset clears LK 0b Register can be written 1b Register cannot be written until the next system Reset 30 24 SEL3 Trigger MUX Input 3 Source Select...

Page 395: ...field is used to configure the MUX select for peripheral trigger input 0 For the field setting definitions see Memory map and register definition 17 4 1 11 TRGMUX FTM3 Register FTM3 17 4 1 11 1 Offset...

Page 396: ...to configure the MUX select for peripheral trigger input 2 For the field setting definitions see Memory map and register definition 15 This read only bit field is reserved and always has the value 0...

Page 397: ...t system Reset 30 24 This read only bit field is reserved and always has the value 0 23 This read only bit field is reserved and always has the value 0 22 16 This read only bit field is reserved and a...

Page 398: ...ystem reset Once LK is set the SELx bits in this TRGMUX register cannot be changed until the next system reset clears LK 0b Register can be written 1b Register cannot be written until the next system...

Page 399: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R LK SEL3 0 SEL2 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SEL1 0 SEL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 400: ...it field is reserved and always has the value 0 14 8 SEL1 Trigger MUX Input 1 Source Select This read write bit field is used to configure the MUX select for peripheral trigger input 1 For the field s...

Page 401: ...e Memory map and register definition 23 This read only bit field is reserved and always has the value 0 22 16 SEL2 Trigger MUX Input 2 Source Select This read write bit field is used to configure the...

Page 402: ...tten or not The LK bit can only be written once after any system reset Once LK is set the SELx bits in this TRGMUX register cannot be changed until the next system reset clears LK 0b Register can be w...

Page 403: ...17 TRGMUX LPUART1 Register LPUART1 17 4 1 17 1 Offset Register Offset LPUART1 50h 17 4 1 17 2 Function This register is for the LPUART1 module 17 4 1 17 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21...

Page 404: ...eserved and always has the value 0 15 This read only bit field is reserved and always has the value 0 14 8 This read only bit field is reserved and always has the value 0 7 This read only bit field is...

Page 405: ...system Reset 30 24 This read only bit field is reserved and always has the value 0 23 This read only bit field is reserved and always has the value 0 22 16 This read only bit field is reserved and alw...

Page 406: ...system reset Once LK is set the SELx bits in this TRGMUX register cannot be changed until the next system reset clears LK 0b Register can be written 1b Register cannot be written until the next syste...

Page 407: ...Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R LK 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 SEL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 408: ...field is reserved and always has the value 0 7 This read only bit field is reserved and always has the value 0 6 0 SEL0 Trigger MUX Input 0 Source Select This read write bit field is used to configure...

Page 409: ...system Reset 30 24 This read only bit field is reserved and always has the value 0 23 This read only bit field is reserved and always has the value 0 22 16 This read only bit field is reserved and alw...

Page 410: ...system reset Once LK is set the SELx bits in this TRGMUX register cannot be changed until the next system reset clears LK 0b Register can be written 1b Register cannot be written until the next syste...

Page 411: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R LK 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 SEL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 4...

Page 412: ...bit field is reserved and always has the value 0 7 This read only bit field is reserved and always has the value 0 6 0 SEL0 Trigger MUX Input 0 Source Select This read write bit field is used to confi...

Page 413: ...t system Reset 30 24 This read only bit field is reserved and always has the value 0 23 This read only bit field is reserved and always has the value 0 22 16 This read only bit field is reserved and a...

Page 414: ...ystem reset Once LK is set the SELx bits in this TRGMUX register cannot be changed until the next system reset clears LK 0b Register can be written 1b Register cannot be written until the next system...

Page 415: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R LK 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 SEL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 4...

Page 416: ...bit field is reserved and always has the value 0 14 8 This read only bit field is reserved and always has the value 0 7 This read only bit field is reserved and always has the value 0 6 0 SEL0 Trigger...

Page 417: ...et s attached to the Reference Manual 18 1 2 EWM Memory Map access Only 8 bit access is supported 18 1 3 EWM low power modes This table shows the EWM low power modes and the corresponding chip low pow...

Page 418: ...ffers from the internal watchdog in that it does not reset the MCU s CPU and peripherals The EWM provides an independent EWM_OUT_b signal that when asserted resets or places an external circuit into a...

Page 419: ...from the same value prior to entry to stop mode Note the following if the EWM enters the stop mode during CPU refresh mechanism At the exit from stop mode by an interrupt refresh mechanism state mach...

Page 420: ...U Reset Figure 18 1 EWM Block Diagram 18 3 EWM Signal Descriptions The EWM has two external signals as shown in the following table NOTE All active low signals are now represented with the suffix _b t...

Page 421: ...006_1000h Offset Register Width In bits Access Reset value 0h Control Register CTRL 8 RW 00h 1h Service Register SERV 8 WORZ 00h 2h Compare Low Register CMPL 8 RWONC E 00h 3h Compare High Register CMP...

Page 422: ...bit by writing 0 2 INEN Input Enable This bit when set enables the EWM_in port 1 ASSIN EWM_in s Assertion State Select Default assert state of the EWM_in signal is logic zero Setting the ASSIN bit inv...

Page 423: ...either of the following conditions is true The first or second data byte is not written correctly The second data byte is not written within a fixed number of peripheral bus cycles of the first data...

Page 424: ...ield after a CPU reset even if the default minimum refresh time is required 18 4 1 5 Compare High Register CMPH 18 4 1 5 1 Offset Register Offset CMPH 3h 18 4 1 5 2 Function The CMPH register is reset...

Page 425: ...this field after a CPU reset even if the default maximum refresh time is required 18 4 1 6 Clock Prescaler Register CLKPRESCALER 18 4 1 6 1 Offset Register Offset CLKPRESCALER 5h 18 4 1 6 2 Function T...

Page 426: ...US_CLK is lost then EWM module doesn t generate the EWM_OUT_b signal and no refresh operation is possible 18 5 1 The EWM_OUT_b Signal The EWM_OUT_b is a digital output signal used to gate an external...

Page 427: ...own state when EWM functionality is used and when EWM is under Reset 18 5 2 EWM_OUT_b pin state in low power modes During Wait Stop and Power Down modes the EWM_OUT_b pin preserve its state before ent...

Page 428: ...k source should be in the kHz range The counter is reset to zero after the CPU reset or when EWM refresh action completes or at counter overflow The counter value is not accessible to the CPU 18 5 5 E...

Page 429: ...e EWM counter is reset to zero and the EWM_OUT_b output signal is asserted irrespective of the input EWM_in signal 18 5 7 EWM Interrupt When EWM_OUT_b is asserted an interrupt request is generated to...

Page 430: ...Functional Description MWCT101xS Series Reference Manual Rev 3 07 2019 430 NXP Semiconductors...

Page 431: ...e following table shows the channel assignments Table 19 1 RAM array targets of EIM channels EIM channel RAM array target 0 SRAM_L 1 SRAM_U 19 2 Introduction The Error Injection Module EIM is mainly u...

Page 432: ...C function of the related system NOTE The following diagram shows an example of EIM implementation with a 64 bit read data bus and an 8 bit checkbit bus Module rdata 63 MSB rdata 62 rdata 61 rdata 0 L...

Page 433: ...addresses Attempted updates to the programming model while the EIM is in the midst of an operation result in non deterministic behavior Error injection channel descriptor function and structure Each e...

Page 434: ...001_9000h Offset Register Width In bits Access Reset value 0h Error Injection Module Configuration Register EIMCR 32 RW 0000_0000h 4h Error Injection Channel Enable register EICHEN 32 RW 0000_0000h 10...

Page 435: ...E N W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 3 2 4 Fields Field Function 31 1 Reserved 0 GEIEN Global Error Injection Enable This bit globally enables or disables the error injection function of the...

Page 436: ...le EIMCR GEIEN field must also be asserted to enable error injection After error injection is enabled all subsequent read accesses incur one or more bit inversions as defined in the corresponding EICH...

Page 437: ...esponding EICHEN EICHnEN field disabling the error injection channel 0b Error injection is disabled on Error Injection Channel 1 1b Error injection is enabled on Error Injection Channel 1 29 Reserved...

Page 438: ...rved 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 Reserved 19 3 4 Error Injection Channel Descriptor n Word0 EICHD0_W ORD0 EICHD1_WORD0 19 3 4 1 Offset Register Offset EICHD0_WORD0 100h EICHD1_WORD0...

Page 439: ...ponding bit of the checkbit bus from the target RAM should be inverted or remain unmodified For any unique details about the mapping of CHKBIT_MASK s bits to a channel s target RAM see the chip specif...

Page 440: ...the read data bus Each bit specifies whether the corresponding bit of the read data bus from the target RAM should be inverted or remain unmodified on read accesses A successful write to this field c...

Page 441: ...nism for a channel Write 1 to the EICHEN EICHnEN field where n denotes the channel number Write 1 to EIMCR GEIEN NOTE When the use case for a channel requires writing any EICHDn_WORD register write th...

Page 442: ...ndefined behavior See below pseudocode Program the one to two bits of the data bus to invert EICHDx_WORDy Enable the channel to allow data inversions EICHxEN Enable the EIM module global enable to sta...

Page 443: ...ghout this chapter Memory n designates the memory array sourced by ERM channel n Introduction 20 2 1 Overview The Error Reporting Module ERM provides information and optional interrupt notification on...

Page 444: ...ing only 32 bit word accesses Any of the following attempted references to the programming model generates an IPS error termination In user mode Using non 32 bit access sizes Attempted accesses to und...

Page 445: ...l register configures the interrupt notification capability for Channel 0 Channel 1 20 3 2 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R ESCIE 0 ENCIE0 0 ESCIE 1 ENCIE1 0 Reserved 0...

Page 446: ...erved 27 ESCIE1 ESCIE1 Enable Memory 1 Single Correction Interrupt Notification This field is initialized by hardware reset NOTE See the chip specific ERM information for details on Memory 1 mapping 0...

Page 447: ...3 3 ERM Status Register 0 SR0 20 3 3 1 Offset Register Offset SR0 10h 20 3 3 2 Function This 32 bit control register configures the interrupt notification capability for Channel 0 Channel 1 Chapter 20...

Page 448: ...ent on Memory 0 detected 30 NCE0 NCE0 Memory 0 Non Correctable Error Event This field is initialized by hardware reset Write 1 to clear this field This write also clears the corresponding interrupt no...

Page 449: ...ENCIE1 is enabled NOTE See the chip specific ERM information for details on Memory 1 mapping 0b No non correctable error event on Memory 1 detected 1b Non correctable error event on Memory 1 detected...

Page 450: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R EAR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 3 4 4 Fields Field Function 31 0 EAR EAR Memory n Error Address This field contains the faulting system address of t...

Page 451: ...Subsequently when a single bit correction event on Memory n is detected the ERM Records the event and address as usual Additionally sends an interrupt notification corresponding to the event 3 To cle...

Page 452: ...To clear both the record of an event and the corresponding interrupt notification write 1 to SRx NCEn to change its value to 0 20 5 Initialization For each ERM channel prepare the corresponding memor...

Page 453: ...ead value can vary depending on timestamp since it is a default running counter 21 1 2 WDOG low power modes This table shows the WDOG low power modes and the corresponding chip low power modes Wait mo...

Page 454: ...DOG after some delay delay configurable within RCM and fixed within WDOG The WDG feature is controlled by WDOG CS whereas RGM feature is controlled by RCM SRIE The delay durations are different For WD...

Page 455: ...lock Programmable timeout period Programmable 16 bit timeout value Optional fixed 256 clock prescaler when longer timeout periods are needed Robust write sequence for counter refresh Refresh sequence...

Page 456: ...le MUX MUX MUX ERCLK external reference clock UPDATE EN CLK PRES WIN INT BUS_CLK 256 16 bit Window Register 0xD928 0xC520 Control Status Bus Cycle Disable Protect Bit Write Control Protect Window Rese...

Page 457: ...Register Offset CS 0h 21 3 1 2 2 Function This section describes the function of Watchdog Control and Status Register NOTE TST is cleared 0 0 on POR only Any other reset does not affect the value of...

Page 458: ...aling of watchdog counter reference clock The block diagram shows this clock divider option 0b 256 prescaler disabled 1b 256 prescaler enabled 11 ULK Unlock status This read only bit indicates whether...

Page 459: ...he watchdog section This write once field is cleared 0 0 on POR only Any other reset does not affect the value of this field 00b Watchdog test mode disabled 01b Watchdog user mode enabled Watchdog tes...

Page 460: ...quence allows the watchdog to be reconfigured without forcing a reset when CS UPDATE 1 See the Configure for reconfigurable section NOTE All other writes to this register are illegal and force a reset...

Page 461: ...ggering event NOTE Do not write 0 to the TOVAL register if CS TST 11b then TOVALHIGH cannot be written as 0 if CS TST 10b then TOVALLOW cannot be 0 otherwise the watchdog always generates a reset 21 3...

Page 462: ...refresh sequence is considered valid See the Watchdog refresh mechanism section The WIN register value must be less than the TOVAL register value 21 3 1 5 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22...

Page 463: ...programming CS CLK bus clock Low Power Oscillator clock LPO_CLK internal clock external clock The options allow software to select a clock source independent of the bus clock for applications that ne...

Page 464: ...after the configuration time period 128 bus clocks ends This delay ensures a smooth transition before restarting the counter with the new configuration 21 4 2 Watchdog refresh mechanism The watchdog r...

Page 465: ...are early When Window mode is enabled the watchdog must be refreshed after the counter has reached a minimum expected time value otherwise the watchdog resets the MCU The minimum expected time value...

Page 466: ...s a robust mechanism to configure the watchdog and ensure that a runaway condition cannot mistakenly disable or modify the watchdog configuration after configured The new configuration takes effect on...

Page 467: ...ing event like a counter timeout or invalid refresh attempt the watchdog first generates an interrupt request Next the watchdog delays 128 bus clocks from the interrupt vector fetch not the reset trig...

Page 468: ...ction 21 4 7 Fast testing of the watchdog Before executing application code in safety critical applications users are required to test that the watchdog works as expected and resets the MCU Testing ev...

Page 469: ...es a reset 5 Confirm the WDOG flag in the system reset register is set indicating that the watchdog caused the reset The POR flag remains clear 6 Confirm that CS TST shows a test 10b or 11b was perfor...

Page 470: ...ring the initial configuration of the WDOG module Then the unlock sequence can be used at any time within the timeout limit to reconfigure the watchdog 21 5 1 Disable Watchdog To disable the watchdog...

Page 471: ..._WIN 0 WDOG_CS_UPDATE 0 while WDOG_CS RCS 0 wait until new configuration takes effect EnableInterrupts enable global interrupt Configure for reconfigurable DisableInterrupts disable global interrupt W...

Page 472: ...Application Information MWCT101xS Series Reference Manual Rev 3 07 2019 472 NXP Semiconductors...

Page 473: ...ts of data at a time 22 2 1 Features Features of the CRC module include Hardware CRC generator circuit using a 16 bit or 32 bit programmable shift register Programmable initial seed value and polynomi...

Page 474: ...22 2 3 Modes of operation Various MCU modes affect the CRC module s functionality 22 2 3 1 Run mode This is the basic mode of operation 22 2 3 2 Low power modes Stop Any CRC calculation in progress st...

Page 475: ...n 16 bit CRC mode the HU and HL fields are not used for programming the seed value and reads of these fields return an indeterminate value In 32 bit CRC mode all fields are used for programming the se...

Page 476: ...C is 0 this field is not used for programming a seed value In 32 bit CRC mode CTRL TCRC is 1 values written to this field are part of the seed value when CTRL WAS is 1 When CTRL WAS is 0 data written...

Page 477: ...20 19 18 17 16 R HIGH W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R LOW W Reset 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 22 3 1 3 4 Fields Field Function 31 16 HIGH High...

Page 478: ...nsposed no bits in a byte are transposed 29 28 TOTR Type Of Transpose For Read Identifies the transpose configuration of the value read from the CRC Data register See the description of the transpose...

Page 479: ...einitialized for a new CRC computation by reasserting CRC_CTRL WAS and programming a new or previously used seed value All other parameters must be set before programming the seed value and subsequent...

Page 480: ...3 Write a 32 bit polynomial to CRC_GPOLY HIGH LOW 4 Set CRC_CTRL WAS to program the seed value 5 Write a 32 bit seed to CRC_DATA HU HL LU LL 6 Clear CRC_CTRL WAS to start writing data values 7 Write...

Page 481: ...lowing types of transpose functions are available for writing to and reading from the CRC data register 1 CTRL TOT or CTRL TOTR is 00 No transposition occurs 2 CTRL TOT or CTRL TOTR is 01 Bits in a by...

Page 482: ...nd using transpose options 10 and 11 the resulting value after transposition resides in the CRC HU HL fields The user software must account for this situation when reading the 16 bit CRC result so rea...

Page 483: ...sses basic reset mechanisms and sources Some peripheral modules that cause resets can be configured to cause interrupts instead See the individual module chapters for more information Each reset sourc...

Page 484: ...em reset sources Resetting the MCU provides a way to start processing from a known set of initial conditions System reset begins with the on chip regulator in full regulation and system clocking gener...

Page 485: ...The pulses upto 2 LPO128K_CLK cycles will always be filtered The pulses longer than 3 LPO128K_CLK cycles will always get passed and generate a RESET The pulses in between 2 to 3 LPO128K_CLK cycles ma...

Page 486: ...ting 1 to SOSCCMRE If the error bit SOSCERR is written to 1 and LOC reset is enabled as mentioned above the MCU resets The MCU writes 1 to the LOC field to indicate this reset source NOTE To prevent u...

Page 487: ...or components except for the debug module A software reset causes the MCU to write 1 to RCM_SRS SW field 23 2 2 8 Lockup reset LOCKUP The LOCKUP gives an immediate indication of seriously errant kerne...

Page 488: ...reset asserts on all reset sources It resets only the flash memory module It deasserts before flash memory initialization begins earlier than the chip reset deassertion 23 2 3 4 Chip reset Chip reset...

Page 489: ...instructions are active The reset source from the JTAG module is released when any other IR code is selected A JTAG reset causes the MCU to write 1 to RCM_SRS JTAG field 23 2 5 2 Resetting the debug s...

Page 490: ...o transfer data into its own message buffers then the DMA module can be used to move the data into the main system RAM Once the download is completed the core can be used to transfer the new downloade...

Page 491: ...MI function is not required either for an interrupt or wake up source it is recommended that the NMI function be disabled by writing 0 to NMI_PIN_CFG 1 NMI_b pin interrupts reset default to enabled 1...

Page 492: ...al drive in low the system continues to be held in reset Once the RESET_B pin is detected high the core clock is enabled and the system is released from reset 6 When the system exits reset the process...

Page 493: ...ice See Module operation in available power modes for details on available power modes LPO128K_CLK is used as low power clock for reset pin filter See Arm Cortex M4 Devices Generic User Guide for deta...

Page 494: ...em Reset Status Register RCM_SRS 32 R 0000_0082h 24 4 3 498 4007_F00C Reset Pin Control register RCM_RPC 32 R W 0000_0000h 24 4 4 501 4007_F018 Sticky System Reset Status Register RCM_SSRS 32 R W 0000...

Page 495: ...read only field returns the minor version number for the specification FEATURE Feature Specification Number This read only field returns the feature set number 0x0003 Standard feature set Chapter 24 R...

Page 496: ...ESW ELOCKUP EJTAG EPOR EPIN EWDOG ECMU_LOC ELOL ELOC ELVD EWAKEUP W Reset 0 0 1 0 1 1 1 1 1 1 1 0 1 1 1 0 RCM_PARAM field descriptions Field Description 31 17 Reserved This field is reserved This read...

Page 497: ...This static bit states whether or not the feature is available on the device 0 The feature is not available 1 The feature is available 10 ESW Existence of SRS SW status indication feature This static...

Page 498: ...feature is available 2 ELOC Existence of SRS LOC status indication feature This static bit states whether or not the feature is available on the device 0 The feature is not available 1 The feature is...

Page 499: ...Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 RCM_SRS field descriptions Field Description 31 17 Reserved This field is reserved This read only field is reserved and always has the value 0 16 Reserved This fi...

Page 500: ...SETREQ bit 1 Reset caused by software setting of SYSRESETREQ bit 9 LOCKUP Core Lockup Indicates a reset has been caused by the Arm core indication of a LOCKUP event 0 Reset not caused by core LOCKUP e...

Page 501: ...ock 1 LVD Low Voltage Detect Reset or High Voltage Detect Reset If PMC_LVDSC1 LVDRE is set and the supply drops below the LVD trip voltage an LVD reset occurs If PMC_HVDSC1 HVDRE is set and the supply...

Page 502: ...d Transition lengths greater than RSTFLTSEL 1 cycles are not filtered 7 3 Reserved This field is reserved This read only field is reserved and always has the value 0 2 RSTFLTSS Reset Pin Filter Select...

Page 503: ...LOC SLVD 0 W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 RCM_SSRS field descriptions Field Description 31 17 Reserved This field is reserved This read only field...

Page 504: ...Reset caused by software setting of SYSRESETREQ bit 9 SLOCKUP Sticky Core Lockup Indicates a reset has been caused by the Arm core indication of a LOCKUP event 0 Reset not caused by core LOCKUP event...

Page 505: ...by a loss of external clock 1 SLVD Sticky Low Voltage Detect Reset If PMC_LVDSC1 LVDRE is set and the supply drops below the LVD trip voltage an LVD reset occurs This field is also set by POR 0 Reset...

Page 506: ...ays has the value 0 14 Reserved This field is reserved This read only field is reserved and always has the value 0 13 SACKERR Stop Acknowledge Error Interrupt 0 Interrupt disabled 1 Interrupt enabled...

Page 507: ...0 Interrupt disabled 1 Interrupt enabled 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 LOL Loss of Lock Interrupt 0 Interrupt disabled 1 Interrupt en...

Page 508: ...Reset memory map and register descriptions MWCT101xS Series Reference Manual Rev 3 07 2019 508 NXP Semiconductors...

Page 509: ...clock dividers and selectors allowing different modules to be clocked at a frequency specific for that module Clock generation logic also implements module specific clock gating allowing modules to b...

Page 510: ...FIRCDIV FIRCDIV2 DIV1 DIV2 SCG_SIRCDIV SIRCDIV1 SCG_SIRCDIV SIRCDIV2 SCG_CLKOUT SCG_SOSCDIV SOSCDIV1 SCG_SOSCDIV SOSCDIV2 SCG_xCCR DIVSLOW DIVSLOW SCG_xCCR DIVBUS DIVBUS SCG_xCCR DIVCORE DIVCORE SPLL_...

Page 511: ...POCLKS CLK32SEL A fixed divide by 4 of LPO_CLK drives 01b input of RTC_CLK multiplexer Source clock for RTC LPO128K_CLK Always on low power oscillator clock generated by PMC SCG_CLKOUT SCG_CLKOUTCNFG...

Page 512: ...RUN mode SOSCDIV2_CLK SCG_SPLLDIV SOSCDIV2 1 2 4 8 16 32 64 or output disabled Divided SOSC_CLK This should be configured to 40 MHz or less in RUN HSRUN mode 1 Only available in MWCT1016S 2 SYS_CLK CO...

Page 513: ...CCR DIVSLOW 0001b Table 25 2 Slow RUN example Clock Frequency CORE_CLK 48 MHz SYS_CLK 48 MHz BUS_CLK 48 MHz max freq in RUN mode FLASH_CLK 24 MHz Option 2 Normal RUN with VCO_CLK 320 MHz SPLL_CLK 160...

Page 514: ...5 High Speed RUN example Clock Frequency CORE_CLK 112 MHz SYS_CLK 112 MHz BUS_CLK 56 MHz FLASH_CLK 28 MHz NOTE All frequencies listed in table above are maximum for HSRUN mode Option 5 High Speed RUN...

Page 515: ...US_CLK 4 MHz FLASH_CLK 1 MHz Following table summarizes the maximum frequencies and example configurations for each internal clock Clock HSRUN RUN VLPR Notes CORE_CLK SYS_CLK 112 MHz 80 MHz 4 MHz Must...

Page 516: ...al to 112MHz BUS_CLK is less than or equal to 56 MHz FLASH_CLK is less than or equal to 28 MHz 25 4 3 VLPR mode clocking Clock dividers should not be modified while the chip is operating in VLPR mode...

Page 517: ...ock Additonal clocks2 Comments and maximum frequencies Gated by CGC of PCC Clocks controlled by PCS of PCC Communications LPUART BUS_CLK Yes SPLLDIV2_CLK FIRCDIV2_CLK SIRCDIV2_CLK SOSCDIV2_CLK Maximum...

Page 518: ...Yes RTC_CLK2 LPO1K_CLK Maximum frequency governed by BUS_CLK PDB SYS_CLK Yes Maximum frequency governed by SYS_CLK FlexTimer SYS_CLK Yes SPLLDIV1_CLK FIRCDIV1_CLK SIRCDIV1_CLK SOSCDIV1_CLK RTC_CLK2 SY...

Page 519: ...y governed by BUS_CLK DMAMUX BUS_CLK Yes Maximum frequency governed by BUS_CLK DMA SYS_CLK No Maximum frequency governed by SYS_CLK MPU SYS_CLK No Maximum frequency governed by SYS_CLK EIM SYS_CLK No...

Page 520: ...L FASTACC 1 FlexIO peripheral clock can be twice of FlexIO Bus interface clock 4 LPO_CLK is the output from the multiplexer that uses SIM_LPOCLKS LPOCLKSEL for source selection See Figure 1 for detail...

Page 521: ...lock gate enable PCC_ module CGC where 1b clock enabled BUS_CLK to module PDB PCC module Clock gate enable PCC_ module CGC where 1b clock enabled SYS_CLK to module DMAMUX CMP0 CRC PCC module Clock gat...

Page 522: ...bus clock FlexCAN SYS_CLK FlexCANn module 0 1 Clock gate enable PCC_FLEXCANn CGC where 1 clock enabled PCC module Module Clock SOSCDIV2_CLK SYS_CLK CAN_CTRL1 CLKSRC CHI Clock PE Clock EIM ERM MSCM DMA...

Page 523: ...power clock Peripheral bus clock WDOG SOSC_CLK SIRC_CLK WDOG module BUS_CLK LPO_CLK WDOG_CS CLK 00 01 10 11 WDOG clock bus_clk bus_clk internal LPO clk internal clk external clk SIM_LPOCLKS LPOCLKSEL...

Page 524: ...RW 00 01 10 11 lpo clock Filter BUS_CLK LPO128K_CLK Reserved System RAM memory clock System RAM SYS_CLK FTFC FLASH_CLK FTFC Clock gate enable PCC_FTFC CGC where 1 clock enabled PCC module Table contin...

Page 525: ...clock enabled SIM_FTMOPT0 FTMnCLKSEL SOSCDIV1_CLK SIRCDIV1_CLK SPLLDIV1_CLK FIRCDIV1_CLK 000 001 010 011 100 101 110 111 Reserved Reserved Reserved PCC_FLEXTMRn PCS 00 01 10 11 TCLK0 TCLK1 TCLK2 Exte...

Page 526: ...0 LPTRM_ALT1 LPTRM_ALT2 LPTRM_ALT3 LPTMR0_PSR PRESCALE LPTMR_PSR PBYP 0 1 Pulse Counter Divider PCC_LPTMR0 PCD Prescaler glitch filter clock0 Prescaler glitch filter clock1 Prescaler glitch filter clo...

Page 527: ...K SFIF_B_CLK 0 1 QuadSPI_MCR SCLKCFG 6 QuadSPI_AHB_Buffer QuadSPI Memory 128x7 1 KB PREDIV_SYS_CLK SYS_CLK 0 1 QuadSPI_MCR SCLKCFG 4 SPLLDIV1 FIRCDIV1 Clock gate enable1 Programmable Divider2 Clock ga...

Page 528: ...Module clocks MWCT101xS Series Reference Manual Rev 3 07 2019 528 NXP Semiconductors...

Page 529: ...IRCSTEN bit field is not applicable and should be ignored 26 1 1 Supported frequency ranges This section describes the supported frequency ranges 1 SCG_SOSCCFG RANGE 00 Reserved 01 Reserved 10 Medium...

Page 530: ...tem clock switching For any clock switching of system clock follow the below steps Before doing a clock switch configure all reset sources to be Reset not as Interrupt via RCM_SRIE Program each reset...

Page 531: ...ule provides the system clocks of the MCU The SCG contains a system phase locked loop SPLL a slow internal reference clock SIRC a fast internal reference clock FIRC and the system oscillator clock SOS...

Page 532: ...for SPLL SOSC clocks Lock detector with interrupt request capability for use with the SPLL Each of the clock sources have reference dividers for clocking on chip modules and peripherals namely SPLLDI...

Page 533: ...SIRCCSR 32 R W 0100_0005h 26 3 11 550 4006_4204 Slow IRC Divide Register SCG_SIRCDIV 32 R W 0000_0000h 26 3 12 551 4006_4208 Slow IRC Configuration Register SCG_SIRCCFG 32 R W 0000_0001h 26 3 13 552 4...

Page 534: ...1 27 DIVPRES Divider Present Indicates which system clock dividers are present in this instance of SCG DIVPRES 27 1 System DIVSLOW is present DIVPRES 28 1 System DIVBUS is present DIVPRES 31 1 System...

Page 535: ...r div by 2 when resetting into RUN mode or div by 4 or div by 8 when resetting into VLPR mode SCG_CSR field descriptions Field Description 31 28 Reserved This field is reserved This read only field is...

Page 536: ...Clock Divide Ratio 0000 Divide by 1 0001 Divide by 2 0010 Divide by 3 0011 Divide by 4 0100 Divide by 5 0101 Divide by 6 0110 Divide by 7 0111 Divide by 8 1000 Divide by 9 1001 Divide by 10 1010 Divi...

Page 537: ...0 SCS 0 DIVCORE Reserved 0 DIVBUS DIVSLOW W Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Notes DIVCORE field The reset value is controlled by user FOPT bits that get uploaded during...

Page 538: ...tware should write 0 to these bits to maintain compatibility This field is reserved 11 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 4 DIVBUS Bus Cloc...

Page 539: ...tios will not take affect until new clock source is valid Address 4006_4000h base 18h offset 4006_4018h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SC...

Page 540: ...by 6 0110 Divide by 7 0111 Divide by 8 1000 Divide by 9 1001 Divide by 10 1010 Divide by 11 1011 Divide by 12 1100 Divide by 13 1101 Divide by 14 1110 Divide by 15 1111 Divide by 16 15 12 Reserved Thi...

Page 541: ...and bus clock domains when in HSRUN mode only This register can only be written using a 32 bit write Selecting a different clock source when in HSRUN requires that clock source to be enabled first and...

Page 542: ...reserved and always has the value 0 19 16 DIVCORE Core Clock Divide Ratio 0000 Divide by 1 0001 Divide by 2 0010 Divide by 3 0011 Divide by 4 0100 Divide by 5 0101 Divide by 6 0110 Divide by 7 0111 Di...

Page 543: ...Divide by 8 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved 26 3 7 SCG CLKOUT Configuration Register SCG_CLKOUTCNFG This register contro...

Page 544: ...ts the SCG system clock 0000 SCG SLOW Clock 0001 System OSC SOSC_CLK 0010 Slow IRC SIRC_CLK 0011 Fast IRC FIRC_CLK 0100 Reserved 0101 Reserved 0110 System PLL SPLL_CLK 0111 Reserved 1111 Reserved Rese...

Page 545: ...is flag is reset on Chip POR only SCG_SOSCCSR field descriptions Field Description 31 27 Reserved This field is reserved This read only field is reserved and always has the value 0 26 SOSCERR System O...

Page 546: ...r Enables the clock monitor when SOSCVLD is set If the clock source is disabled in a low power mode then the clock monitor is also disabled in the low power mode When the clock monitor is disabled in...

Page 547: ...is reserved and always has the value 0 18 16 Reserved This field is reserved This bit field is reserved Software should write 0 to this bit field to maintain compatibility 15 11 Reserved This field is...

Page 548: ...0 Reserved 0 RANGE HGO EREFS 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 SCG_SOSCCFG field descriptions Field Description 31 12 Reserved This field is reserved This read only field is reserved and alway...

Page 549: ...oscillator for high gain operation 2 EREFS External Reference Select Selects the source for the external reference clock This bit selects which clock is output from the System OSC SOSC into the SCG th...

Page 550: ...descriptions Field Description 31 26 Reserved This field is reserved This read only field is reserved and always has the value 0 25 SIRCSEL Slow IRC Selected 0 Slow IRC is not the system clock source...

Page 551: ...Slow IRC is enabled 26 3 12 Slow IRC Divide Register SCG_SIRCDIV To prevent glitches to the output divided clock change SIRDIV when the Slow IRC is disabled Address 4006_4000h base 204h offset 4006_4...

Page 552: ...ock source 000 Output disabled 001 Divide by 1 010 Divide by 2 011 Divide by 4 100 Divide by 8 101 Divide by 16 110 Divide by 32 111 Divide by 64 26 3 13 Slow IRC Configuration Register SCG_SIRCCFG Th...

Page 553: ...range clock 8 MHz 26 3 14 Fast IRC Control Status Register SCG_FIRCCSR Address 4006_4000h base 300h offset 4006_4300h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 FIRCERR FIRCSEL FIRCVLD LK...

Page 554: ...leared set at any time 0 Control Status Register can be written 1 Control Status Register cannot be written 22 10 Reserved This field is reserved This read only field is reserved and always has the va...

Page 555: ...compatibility 15 11 Reserved This field is reserved This read only field is reserved and always has the value 0 10 8 FIRCDIV2 Fast IRC Clock Divide 2 Clock divider 2 for the Fast IRC Used by modules t...

Page 556: ...t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 RANGE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCG_FIRCCFG field descriptions Field Description 31 2 Reserved This field...

Page 557: ...n Chip POR only software can also clear this flag by writing a logic one NOTE The LOL Flag is set when the PLL reference is out of range Dunl in datasheet and is constantly modulated such that 3 conse...

Page 558: ...annot be written 22 18 Reserved This field is reserved This read only field is reserved and always has the value 0 17 SPLLCMRE System PLL Clock Monitor Reset Enable 0 Clock Monitor generates interrupt...

Page 559: ...ield to maintain compatibility 15 11 Reserved This field is reserved This read only field is reserved and always has the value 0 10 8 SPLLDIV2 System PLL Clock Divide 2 Clock divider 2 for System PLL...

Page 560: ...SOURCE is the clock source selected from the SOURCE bitfield of this register Address 4006_4000h base 608h offset 4006_4608h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 MULT W Reset 0 0 0...

Page 561: ...0111 23 01111 31 10111 39 11111 47 15 11 Reserved This field is reserved This read only field is reserved and always has the value 0 10 8 PREDIV PLL Reference Clock Divider Selects the amount to divid...

Page 562: ...t mode is not supported on this device Reset SIRC RUN Valid SCG Modes HSRUN Valid SCG Modes FIRC VLPRUN Valid SCG Modes SYS PLL SYS PLL SOSC FIRC SIRC Run Run High Speed Run Very Low Power SCG Valid M...

Page 563: ...CGCLKOUT and system clocks are derived from the external System Oscillator Clock SOSC Slow Internal Reference Clock SIRC Slow Internal Reference Clock SIRC mode is entered when all the following condi...

Page 564: ...to a multiplication factor as specified by its corresponding SCG_SPLLCFG MULT times the selected PLL reference frequency The PLL s programmable reference divider must be configured to produce a valid...

Page 565: ...s in a quiescent state After clock switching the module should be soft reset using soft reset bit module software reset bit if available SIM_SDID FEATURES bit field overrides the PCC PR status for the...

Page 566: ...k option 3 PCS 001 Clock option 4 Clock option 5 Clock option 7 to module functional clock Gate CGC Chip specific clock to module interface clock Divider FRAC PCD OFF External clock 000 Not all module...

Page 567: ...a functional clock the module s interface clock must be disabled CGC 0 27 5 Memory map and register definition Each module has its own dedicated PCC register which controls the clock gating clock sour...

Page 568: ...C RTC Register PCC_RTC 32 RW 8000_0000h 100h PCC LPTMR0 Register PCC_LPTMR0 32 RW 8000_0000h 124h PCC PORTA Register PCC_PORTA 32 RW 8000_0000h 128h PCC PORTB Register PCC_PORTB 32 RW 8000_0000h 12Ch...

Page 569: ...0 0 0 0 0 0 0 0 27 6 2 4 Fields Field Function 31 PR Present This bit shows whether the peripheral is present on this device 0b Peripheral is not present 1b Peripheral is present 30 CGC Clock Gate Co...

Page 570: ...ed and always has the value 0 26 24 This read only bit field is reserved and always has the value 0 23 4 This read only bit field is reserved and always has the value 0 3 This read only bit field is r...

Page 571: ...ivider options can be modified 0b Clock disabled The current clock selection and divider options are not locked and can be modified 1b Clock enabled The current clock selection and divider options are...

Page 572: ...Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 6 4 4 Fields Field Function 31 PR Present This bit shows whether the...

Page 573: ...bit can change values but is a don t care 28 27 This read only bit field is reserved and always has the value 0 26 24 This read only bit field is reserved and always has the value 0 23 4 This read on...

Page 574: ...on and divider options can be modified 0b Clock disabled The current clock selection and divider options are not locked and can be modified 1b Clock enabled The current clock selection and divider opt...

Page 575: ...0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 6 6 4 Fields Field Function 31 PR Present This bit shows whether the peripheral is...

Page 576: ...ct This read write bit field is used for peripherals that support various clock selections This field can be written only when the clock is disabled CGC 0 000b Clock is off An external clock can be en...

Page 577: ...Clock disabled The current clock selection and divider options are not locked and can be modified 1b Clock enabled The current clock selection and divider options are locked and cannot be modified 29...

Page 578: ...PCC FlexCAN2 Register PCC_FlexCAN2 27 6 8 1 Offset Register Offset PCC_FlexCAN2 ACh 27 6 8 2 Function This register is for the FlexCAN2 module 27 6 8 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20...

Page 579: ...ider options are locked and cannot be modified 29 This read only bit field is reserved This bit can change values but is a don t care 28 27 This read only bit field is reserved and always has the valu...

Page 580: ...fied 0b Clock disabled The current clock selection and divider options are not locked and can be modified 1b Clock enabled The current clock selection and divider options are locked and cannot be modi...

Page 581: ...PI1 Register PCC_LPSPI1 27 6 10 1 Offset Register Offset PCC_LPSPI1 B4h 27 6 10 2 Function This register is for the LPSPI1 module 27 6 10 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 582: ...served This bit can change values but is a don t care 28 27 This read only bit field is reserved and always has the value 0 26 24 PCS Peripheral Clock Source Select This read write bit field is used f...

Page 583: ...on this device 0b Peripheral is not present 1b Peripheral is present 30 CGC Clock Gate Control This read write bit enables the interface clock for the peripheral allowing access to the module s regist...

Page 584: ...ff 001b Clock option 1 010b Clock option 2 011b Clock option 3 100b Clock option 4 101b Clock option 5 110b Clock option 6 111b Clock option 7 23 4 This read only bit field is reserved and always has...

Page 585: ...divider options can be modified 0b Clock disabled The current clock selection and divider options are not locked and can be modified 1b Clock enabled The current clock selection and divider options ar...

Page 586: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 6 13 4 Fields Field Function 31 PR Present This bit shows whether the periphe...

Page 587: ...d This bit can change values but is a don t care 28 27 This read only bit field is reserved and always has the value 0 26 24 This read only bit field is reserved and always has the value 0 23 4 This r...

Page 588: ...ion and divider options can be modified 0b Clock disabled The current clock selection and divider options are not locked and can be modified 1b Clock enabled The current clock selection and divider op...

Page 589: ...0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 6 15 4 Fields Field Function 31 PR Present This bit shows whether the peripheral i...

Page 590: ...ipheral Clock Source Select This read write bit field is used for peripherals that support various clock selections This field can be written only when the clock is disabled CGC 0 000b Clock is off 00...

Page 591: ...clock selection and divider options are not locked and can be modified 1b Clock enabled The current clock selection and divider options are locked and cannot be modified 29 This read only bit field i...

Page 592: ...6 17 PCC FTM1 Register PCC_FTM1 27 6 17 1 Offset Register Offset PCC_FTM1 E4h 27 6 17 2 Function This register is for the FTM1 module 27 6 17 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 593: ...but is a don t care 28 27 This read only bit field is reserved and always has the value 0 26 24 PCS Peripheral Clock Source Select This read write bit field is used for peripherals that support vario...

Page 594: ...esent on this device 0b Peripheral is not present 1b Peripheral is present 30 CGC Clock Gate Control This read write bit enables the interface clock for the peripheral allowing access to the module s...

Page 595: ...for this peripheral 001b Clock option 1 010b Clock option 2 011b Clock option 3 100b Clock option 4 101b Clock option 5 110b Clock option 6 111b Clock option 7 23 4 This read only bit field is reserv...

Page 596: ...lock disabled The current clock selection and divider options are not locked and can be modified 1b Clock enabled The current clock selection and divider options are locked and cannot be modified 29 T...

Page 597: ...gister PCC_RTC 27 6 20 1 Offset Register Offset PCC_RTC F4h 27 6 20 2 Function This register is for the RTC module 27 6 20 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R P R CGC Rese...

Page 598: ...and divider options are locked and cannot be modified 29 This read only bit field is reserved This bit can change values but is a don t care 28 27 This read only bit field is reserved and always has t...

Page 599: ...0b Clock disabled The current clock selection and divider options are not locked and can be modified 1b Clock enabled The current clock selection and divider options are locked and cannot be modified...

Page 600: ...ock is disabled 0b Fractional value is 0 1b Fractional value is 1 2 0 PCD Peripheral Clock Divider Select This read write bit field is used for peripherals that require a clock divider Divider output...

Page 601: ...divider options can be modified 0b Clock disabled The current clock selection and divider options are not locked and can be modified 1b Clock enabled The current clock selection and divider options ar...

Page 602: ...t 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 6 23 4 Fields Field Function 31 PR Present This bit shows whether the pe...

Page 603: ...This bit can change values but is a don t care 28 27 This read only bit field is reserved and always has the value 0 26 24 This read only bit field is reserved and always has the value 0 23 4 This rea...

Page 604: ...ion and divider options can be modified 0b Clock disabled The current clock selection and divider options are not locked and can be modified 1b Clock enabled The current clock selection and divider op...

Page 605: ...0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 6 25 4 Fields Field Function 31 PR Present This bit shows whether the peripheral...

Page 606: ...eserved This bit can change values but is a don t care 28 27 This read only bit field is reserved and always has the value 0 26 24 This read only bit field is reserved and always has the value 0 23 4...

Page 607: ...divider options can be modified 0b Clock disabled The current clock selection and divider options are not locked and can be modified 1b Clock enabled The current clock selection and divider options ar...

Page 608: ...eset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 6 27 4 Fields Field Function 31 PR Present This bit shows whether the...

Page 609: ...Clock Source Select This read write bit field is used for peripherals that support various clock selections This field can be written only when the clock is disabled CGC 0 000b Clock is off 001b Cloc...

Page 610: ...ion and divider options can be modified 0b Clock disabled The current clock selection and divider options are not locked and can be modified 1b Clock enabled The current clock selection and divider op...

Page 611: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 6 29 4 Fields Field Function 31 PR Present This bit shows whether the perip...

Page 612: ...heral Clock Source Select This read write bit field is used for peripherals that support various clock selections This field can be written only when the clock is disabled CGC 0 000b Clock is off 001b...

Page 613: ...Clock disabled The current clock selection and divider options are not locked and can be modified 1b Clock enabled The current clock selection and divider options are locked and cannot be modified 29...

Page 614: ...CC LPUART0 Register PCC_LPUART0 27 6 31 1 Offset Register Offset PCC_LPUART0 1A8h 27 6 31 2 Function This register is for the LPUART0 module 27 6 31 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20...

Page 615: ...s bit can change values but is a don t care 28 27 This read only bit field is reserved and always has the value 0 26 24 PCS Peripheral Clock Source Select This read write bit field is used for periphe...

Page 616: ...s present on this device 0b Peripheral is not present 1b Peripheral is present 30 CGC Clock Gate Control This read write bit enables the interface clock for the peripheral allowing access to the modul...

Page 617: ...ption 1 010b Clock option 2 011b Clock option 3 100b Clock option 4 101b Clock option 5 110b Clock option 6 111b Clock option 7 23 4 This read only bit field is reserved and always has the value 0 3 T...

Page 618: ...lock disabled The current clock selection and divider options are not locked and can be modified 1b Clock enabled The current clock selection and divider options are locked and cannot be modified 29 T...

Page 619: ...ter PCC_FTM4 27 6 34 1 Offset Register Offset PCC_FTM4 1B8h 27 6 34 2 Function This register is for the FTM4 module 27 6 34 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R P R CGC Res...

Page 620: ...e values but is a don t care 28 27 This read only bit field is reserved and always has the value 0 26 24 PCS Peripheral Clock Source Select This read write bit field is used for peripherals that suppo...

Page 621: ...this device 0b Peripheral is not present 1b Peripheral is present 30 CGC Clock Gate Control This read write bit enables the interface clock for the peripheral allowing access to the module s register...

Page 622: ...enabled for this peripheral 001b Clock option 1 010b Clock option 2 011b Clock option 3 100b Clock option 4 101b Clock option 5 110b Clock option 6 111b Clock option 7 23 4 This read only bit field i...

Page 623: ...ection and divider options are not locked and can be modified 1b Clock enabled The current clock selection and divider options are locked and cannot be modified 29 This read only bit field is reserved...

Page 624: ...TM7 Register PCC_FTM7 27 6 37 1 Offset Register Offset PCC_FTM7 1C4h 27 6 37 2 Function This register is for the FTM7 module 27 6 37 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R P...

Page 625: ...but is a don t care 28 27 This read only bit field is reserved and always has the value 0 26 24 PCS Peripheral Clock Source Select This read write bit field is used for peripherals that support vario...

Page 626: ...sent on this device 0b Peripheral is not present 1b Peripheral is present 30 CGC Clock Gate Control This read write bit enables the interface clock for the peripheral allowing access to the module s r...

Page 627: ...his read only bit field is reserved and always has the value 0 3 This read only bit field is reserved and always has the value 0 2 0 This read only bit field is reserved and always has the value 0 27...

Page 628: ...ion and divider options can be modified 0b Clock disabled The current clock selection and divider options are not locked and can be modified 1b Clock enabled The current clock selection and divider op...

Page 629: ...ash memory modules For details about these modules see Flash Memory Controller FMC Flash Memory Module FTFC 28 3 SRAM configuration This section summarizes how the module has been configured in the ch...

Page 630: ...in the Arm Cortex M4F architecture In the SIM SDID RAMSIZE identifies the total amount of SRAM on a device For each chip in the series the following table shows the size of each SRAM region within tha...

Page 631: ...cycle for write Cortex M4F core Code bus System bus SRAM controller Backdoor SRAM_L SRAM_U Crossbar Switch Non core master Non core master Non core master Frontdoor System MPU System MPU Figure 28 1 S...

Page 632: ...rupt Enable Register RCM_SRIE to delay the reset and instead generate an interrupt on every reset request 2 On an interrupt for a reset request application code configures the chip to enter Run mode a...

Page 633: ...orrectable ECC error event If yes it is recommended to follow the recommended reaction system reset A reset reaction is recommended on receiving an ECC event after doing necessary health checks for sy...

Page 634: ...SRAM configuration MWCT101xS Series Reference Manual Rev 3 07 2019 634 NXP Semiconductors...

Page 635: ...d only 29 1 2 LMEM SRAM sizes SRAM sizes vary across the products in the WCT101xS series In this chapter SRAM Arrays documents the superset SRAM sizes For each WCT101xS product s SRAM sizes and other...

Page 636: ...e local memory controller includes three memory controllers and their attached memories SRAM lower SRAM_L controller via the PC bus SRAM upper SRAM_U controller via the PS bus Cache memory controller...

Page 637: ...s spaces are device specific See the chip specific LMEM information for the address space decode details 29 2 2 Cache features A cache is a block of high speed memory locations containing address info...

Page 638: ...h this cache mode are cacheable If all cacheable spaces are read only spaces the cache will contain read only data and all write to the cache will fault See the chip specific cacheable space informati...

Page 639: ...address E008_2000h Offset Register Width In bits Access Reset value 0h Cache control register PCCCR 32 RW 0000_0000h 4h Cache line control register PCCLCR 32 RW 0000_0000h 8h Cache search address reg...

Page 640: ...o operation 1b When setting the GO bit push all modified lines in way 1 26 INVW1 Invalidate Way 1 NOTE If the PUSHW1 and INVW1 bits are set then after setting the GO bit push all modified lines in way...

Page 641: ...be performed using a specific cache line address or a physical address If a physical address is specified both ways of the cache are searched and the command is only performed on the way which hits 2...

Page 642: ...che address and way then this bit shows the initial state of the modified bit If command used physical address and a hit then this bit shows the initial state of the modified bit If a miss this bit re...

Page 643: ...d active 1b Write initiate line command indicated by bits 27 24 Read line command active 29 3 1 4 Cache search address register PCCSAR 29 3 1 4 1 Offset Register Offset PCCSAR 8h 29 3 1 4 2 Function T...

Page 644: ...a line command is active NOTE This bit stays set until the command completes Writing zero has no effect NOTE This bit is shared with CLCR LGO 0b Write no effect Read no line command active 1b Write in...

Page 645: ...bit CCVR 0 tag valid bit For data search read or write CCVR 31 0 bits are used for data array R W value 29 3 1 6 Cache regions mode register PCCRMR 29 3 1 6 1 Offset Register Offset PCCRMR 20h 29 3 1...

Page 646: ...26 25 24 23 22 21 20 19 18 17 16 R R0 R1 R2 R3 R4 R5 R6 R7 W Reset 1 0 1 0 1 0 1 0 0 0 0 0 1 1 1 1 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R8 R9 R10 R11 R12 R13 R14 R15 W Reset 1 0 1 0 0 0 0 0 0...

Page 647: ...b Non cacheable 01b Non cacheable 10b Write through 11b Write back 17 16 R7 Region 7 mode Controls the cache mode for region 7 00b Non cacheable 01b Non cacheable 10b Write through 11b Write back 15 1...

Page 648: ...00b Non cacheable 01b Non cacheable 10b Write through 11b Write back 3 2 R14 Region 14 mode Controls the cache mode for region 14 00b Non cacheable 01b Non cacheable 10b Write through 11b Write back...

Page 649: ...Memory Controller This controller then processes the cacheable accesses as needed while bypassing the non cacheable cache write through cache miss and cache maintenance accesses to the CCM bus and th...

Page 650: ...M_L and SRAM_U are then defined as SRAM_L 0x20000_0000 128 KBytes to 0x1fff_ffff SRAM_U 0x2000_0000 to 0x2000_0000 128 KBytes SRAML_SIZE and SRAMU_SIZE do not have to be equal 29 4 2 3 SRAM Accesses T...

Page 651: ...ion is controlled by the SRAM controller based on the configuration bits in the MCM module NOTE Burst access cannot occur across the 0x2000_0000 boundary that separates the two SRAM arrays The two arr...

Page 652: ...1 of 128 sets Not Used Address 3 0 Table 29 2 Data Cache Address Use Data Cache Address Use Code Cache Not Used Address 31 11 Data Set Select Address Range Address 10 4 used to select one of 128 sets...

Page 653: ...bit Table 29 3 Cache Set Commands CCR 27 24 Command PUSHW1 INVW1 PUSHW0 INVW0 0 0 0 0 NOP 0 0 0 1 Invalidate all way 0 0 0 1 0 Push all way 0 0 0 1 1 Clear all way 0 0 1 0 0 Invalidate all way 1 0 1 0...

Page 654: ...a physical address the command must also use the CSAR register to specify the physical address A line cache command is initiated by setting the line command go bit CLCR LGO or CSAR LGO This bit also...

Page 655: ...ce the physical address in CSAR PHYADDR and set the line command go bit CSAR LGO When one line command completes initiate the next command by following these steps Increment the physical address at bi...

Page 656: ...Way 0 valid and modified 1 0 0 Way 1 line was invalid No hit 1 0 1 Way 1 valid not modified Way 1 valid not modified 1 1 0 Way 1 line was invalid No hit 1 1 1 Way 1 valid and modified Way 1 valid and...

Page 657: ...For the exact amount of total SRAM see the SIM s SDID RAMSIZE For the exact amounts of SRAM_L and SRAM_U within that total see SRAM sizes NOTE TCMU and TCML terms are interchangeable with SRAM_U and S...

Page 658: ...n Chip Memory Registers MSCM Reset Configuration RCON On Chip Memory Bus Interface to CPU or other Bus Masters Figure 30 1 MSCM Block Diagram 30 3 Chip Configuration and Boot The device s logical defi...

Page 659: ...memory mapped read only addresses defining the processor set up This portion of the MSCM programming model can only be accessed with privileged mode 32 bit read references any other access type or si...

Page 660: ...CP0COUNT 32 RO 0000_0000h 30h Processor 0 Configuration Register 0 CP0CFG0 32 RO 0400_0000h 34h Processor 0 Configuration Register 1 CP0CFG1 32 RO 0000_0000h 38h Processor 0 Configuration Register 2 C...

Page 661: ...30 4 2 2 4 Fields Field Function 31 8 PERSONALITY Processor x Personality This read only field defines the processor personality for CPUx if CPUx Cortex M4 then PERSONALITY 0x43_4D_34 CM4 7 0 RYPZ Pr...

Page 662: ...6 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CPN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u 30 4 2 3 4 Fields Field Function 31 1 Reserved 0 CPN Processor...

Page 663: ...write accesses are terminated with an error 30 4 2 4 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 664: ...Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PCNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 4 2 5 4 Fields Field Function 31 2 Reserved 1 0 PCNT Processor Count This read only field defines the pro...

Page 665: ...ction Cache Size This read only field provides an encoded value of the Instruction Cache size The capacity of the memory is expressed as Size bytes 2 8 ICSZ where ICSZ is non zero a ICSZ 0 indicates t...

Page 666: ...Data Cache then DCSZ 0x06 if a 32 Kbyte Data Cache then DCSZ 0x07 if a 64 Kbyte Data Cache then DCSZ 0x08 7 0 DCWY Level 1 Data Cache Ways This read only field provides the number of cache ways for th...

Page 667: ...a 512 byte Level 2 Cache then L2SZ 0x01 if a 1 Kbyte Level 2 Cache then L2SZ 0x02 if a 2 Kbyte Level 2 Cache then L2SZ 0x03 if a 4 Kbyte Level 2 Cache then L2SZ 0x04 if an 8 Kbyte Level 2 Cache then...

Page 668: ...on 31 24 TMLSZ Tightly coupled Memory Lower Size This field provides an encoded value of the tightly coupled local memory lower size The capacity of the memory is expressed as Size bytes 2 8 TMLSZ whe...

Page 669: ...Z 0x06 if a 32 Kbyte TCMU then TMUSZ 0x07 if a 64 Kbyte TCMU then TMUSZ 0x08 if a 128 Kbyte TCMU then TMUSZ 0x09 7 0 Reserved 30 4 2 9 Processor X Configuration Register 3 CPxCFG3 30 4 2 9 1 Offset Re...

Page 670: ...icates if the core memory protection hardware is included in the processor 0b Core Memory Protection is not included 1b Core Memory Protection is included 4 TZ Trust Zone This field indicates if the T...

Page 671: ...or 0 Type Register CP0TYPE 30 4 2 10 1 Offset Register Offset CP0TYPE 20h 30 4 2 10 2 Function The register provides the personality of Processor 0 The 32 bit response includes 3 ASCII characters defi...

Page 672: ...core release 30 4 2 11 Processor 0 Number Register CP0NUM 30 4 2 11 1 Offset Register Offset CP0NUM 24h 30 4 2 11 2 Function The register provides the logical processor number of Processor 0 The logic...

Page 673: ...Function The register provides the physical bus master number of Processor 0 30 4 2 12 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 1...

Page 674: ...he chip configuration 30 4 2 13 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PCNT W Reset 0...

Page 675: ...2 1 0 R DCSZ DCWY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 4 2 14 4 Fields Field Function 31 24 ICSZ Level 1 Instruction Cache Size This read only field provides an encoded value of the Instruction...

Page 676: ...if a 512 byte Data Cache then DCSZ 0x01 if a 1 Kbyte Data Cache then DCSZ 0x02 if a 2 Kbyte Data Cache then DCSZ 0x03 if a 4 Kbyte Data Cache then DCSZ 0x04 if an 8 Kbyte Data Cache then DCSZ 0x05 if...

Page 677: ...a 512 byte Level 2 Cache then L2SZ 0x01 if a 1 Kbyte Level 2 Cache then L2SZ 0x02 if a 2 Kbyte Level 2 Cache then L2SZ 0x03 if a 4 Kbyte Level 2 Cache then L2SZ 0x04 if an 8 Kbyte Level 2 Cache then...

Page 678: ...es 2 8 TMLSZ where TMLSZ is non zero a TMLSZ 0 indicates the memory is not present if no TCML then TMLSZ 0x00 if a 512 byte TCML then TMLSZ 0x01 if a 1 Kbyte TCML then TMLSZ 0x02 if a 2 Kbyte TCML the...

Page 679: ...ion Register 3 CP0CFG3 30 4 2 17 1 Offset Register Offset CP0CFG3 3Ch 30 4 2 17 2 Function The CP0CFG3 register provides information on Processor 0 options NOTE Reset values for the Processor 0 Config...

Page 680: ...MMU Memory Management Unit Memory Management Unit This field indicates if the virtual memory management capabilities are supported in the processor 0b MMU support is not included 1b MMU support is inc...

Page 681: ...ds from any other bus master return all zeroes Privileged writes from a processor core or the debugger to writeable registers update the appropriate fields Privileged writes from other bus masters are...

Page 682: ...ue of 1 29 Reserved 28 OCMSZH OCMSZH OCMEM Size Hole For on chip memories that are not fully populated that is include a memory hole in the upper 25 of the address range this bit is used 0b OCMEMn is...

Page 683: ...eserved 011b Reserved 100b OCMEMn is a Program Flash 101b OCMEMn is a Data Flash 110b OCMEMn is an EEE 111b Reserved 12 OCMPU OCMPU OCMEM Memory Protection Unit This field is reserved for this device...

Page 684: ...scriptor registers that provide static information about the attached memories as well as configurable controls where appropriate Privileged 32 bit reads from a processor core or the debugger return t...

Page 685: ...nes the validity presence of the on chip memory 0b OCMEMn is not present 1b OCMEMn is present 30 Reserved This Reserved field always has the value of 1 29 Reserved 28 OCMSZH OCMSZH OCMEM Size Hole For...

Page 686: ...vides a mechanism to lock the configuration state defined by OCMDRn 11 0 Once asserted attempted writes to the OCMDRn 11 0 register are ignored until the next reset clears the flag 0b Writes to the OC...

Page 687: ...culation for Data disabled Enabled Enabled Speculation for both Instruction and Data enabled 3 0 Reserved 30 4 2 20 On Chip Memory Descriptor Register OCMDR2 30 4 2 20 1 Offset Register Offset OCMDR2...

Page 688: ...1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 30 4 2 20 4 Fields Field Function 31 V V OCMEM Valid bit This read only field defines the validity presence of the on chip memory 0b OCMEMn is not present 1b OCMEMn is pr...

Page 689: ...its wide 110 111b Reserved 16 RO RO Read Only This register bit provides a mechanism to lock the configuration state defined by OCMDRn 11 0 Once asserted attempted writes to the OCMDRn 11 0 register a...

Page 690: ...Field Function 5 4 Reserved 3 0 Reserved MSCM Memory Map Register Definition MWCT101xS Series Reference Manual Rev 3 07 2019 690 NXP Semiconductors...

Page 691: ...ble power modes for details on available power modes Table 31 1 Reference links to related information Topic Related module Reference System memory map See attached MWCT101xS_memory_map xlsx Clocking...

Page 692: ...rmation to ensure a proper interface The following table shows the supported read write operations Flash memory type Read Write Program flash memory 8 bit 16 bit and 32 bit reads 1 FlexNVM used as Dat...

Page 693: ...exMemory to the device 128 64 for bank1 Data Flash bit prefetch speculation buffer with controls for instruction data access per master and bank Single entry buffer per bank 31 3 Modes of operation Th...

Page 694: ...nd or data For example consider the following scenario Assume a system with a 4 1 core to flash clock ratio and with speculative reads enabled The core requests four for Data Flash bank 1 or eight for...

Page 695: ...k 1 reading the fourth longword like the second longword takes only 1 clock due to the 64 bit flash memory data bus 6 Per 128 bit for Program Flash bank 0 reading the sixth seventh and eighth longword...

Page 696: ...Initialization and application information MWCT101xS Series Reference Manual Rev 3 07 2019 696 NXP Semiconductors...

Page 697: ...rmation Topic Related module Reference System memory map See attached MWCT101xS_memory_map xlsx Clocking System Clock Generator Clock Distribution Transfers Flash Memory Controller Flash Memory Contro...

Page 698: ...12 MHz because this use case is not allowed to execute simultaneously The device need to switch to RUN mode 80 Mhz to execute CSEc Security or EEPROM writes erase 32 1 2 Flash memory sizes TThe FTFC m...

Page 699: ...e Data flash port width For details see FMC chapter 32 1 2 1 512 KB program flash 64 KB FlexNVM 4 KB FlexRAM module MWCT1014S The 512 KB FTFC flash module consists of two NVM read partitions and one F...

Page 700: ...P Flash 48 KB E Flash 4 KB EERAM CSEc Enabled without CSEc remove the PRAM 128 bytes PRAM 512 KB P Flash 64 KB E Flash DEPART configuration command Figure 32 2 512 KB flash memory map 32 1 2 1 1 Emula...

Page 701: ...FlexRAM for emulated EEPROM use NOTE 1 EEESIZE must be 0 bytes 1111b when the FlexNVM partition code is set to No EEPROM 2 For CSEc enabled parts the EEE size must be 0010 4 096 bytes 0000 Reserved 0...

Page 702: ...1 MB program flash 64 KB FlexNVM 4 KB FlexRAM module MWCT1015S The 1 MB FTFC flash module consists of three NVM read partitions and one FlexRAM block Two 512 KB program flash read partitions interlea...

Page 703: ...PART configuration command 1 MB P Flash 1 MB P Flash 1 MB P Flash Figure 32 3 1 MB flash memory map 32 1 2 2 1 Emulated EEPROM data set size EEESIZE Table 32 6 Emulated EEPROM data set size for 4 KB F...

Page 704: ...use NOTE 1 EEESIZE must be 0 bytes 1111b when the FlexNVM partition code is set to No EEPROM 2 For CSEc enabled parts the EEE size must be 0010 4 096 bytes 0000 Reserved 0001 Reserved 0010 4 096 byte...

Page 705: ...itions and one FlexRAM block Three 512 KB program flash read partitions interleaved 2 256 KB 5 One shared Program Data Flash FlexNVM read partition interleaved 2 256 KB 5 This shared read partition co...

Page 706: ...nabled FlexMEM Enabled 1 5 MB P Flash 1 5 MB P Flash 1 5 MB P Flash 448 KB D P Flash 64 KB D Flash 448 KB D P Flash 4 KB EERAM 4 KB EERAM 64 KB E Flash 64 KB E Flash Figure 32 4 2 MB flash memory map...

Page 707: ...Encoding of the total available FlexRAM for emulated EEPROM use NOTE 1 EEESIZE must be 0 bytes 1111b when the FlexNVM partition code is set to No EEPROM 2 For CSEc enabled parts the EEE size must be 0...

Page 708: ...fault value a PGMPART command must be launched for this code to be valid 1 Although this is the default value a PGMPART command must be launched for this code to be valid 32 1 3 Flash memory map The v...

Page 709: ...all contents of flash memory An Erase All Blocks command can be launched by software through a series of peripheral bus writes to FTFC registers In addition the entire flash memory can be erased from...

Page 710: ...xternal high voltage power sources The FTFC module includes a memory controller that executes commands to modify flash memory contents An erased bit reads 1 and a programmed bit reads 0 The programmin...

Page 711: ...to the program flash block is possible while programming or erasing data in the data flash block or FlexRAM 32 2 1 2 FlexNVM memory features When FlexNVM is partitioned for data flash memory Sector si...

Page 712: ...SEc module features The FTFC module includes feature support for the SHE Secure Hardware Extension specification Secure cryptographic key storage ranging from 3 to 17 user keys AES 128 encryption and...

Page 713: ...MCU writes to the Flash FCCOB register group that initiates and controls the execution of Flash algorithms that are built into the FTFC module Cryptographic Services Engine CSEc Feature set for vario...

Page 714: ...ighest endurance EEPROM backup data sector The emulated EEPROM backup data sector contains one emulated EEPROM header and up to 255 emulated EEPROM backup data records which are used by the emulated E...

Page 715: ...flash memory technology NVM Normal Mode An NVM mode that provides basic user access to FTFC resources The CPU or other bus masters initiate flash program and erase operations or other flash commands...

Page 716: ...guration Field Offset Address Size Bytes Field Description 0x0_0400 0x0_0407 8 Backdoor Comparison Key Refer to Verify Backdoor Access Key command and Un securing the MCU using backdoor key access 0x0...

Page 717: ...no program flash IFR erase mechanism available to the user The Program Once field can be read any number of times This section of the program flash 0 IFR is accessed in 8 byte records using the Read O...

Page 718: ...kup memory supporting emulated EEPROM functions To program the DEPART value see the Program Partition command described in Program Partition command Also see the chip specific information Refer to the...

Page 719: ...0h Ch Flash Common Command Object Registers FCCOBB 8 RW 00h Dh Flash Common Command Object Registers FCCOBA 8 RW 00h Eh Flash Common Command Object Registers FCCOB9 8 RW 00h Fh Flash Common Command Ob...

Page 720: ...xRAM while enabled for EEE and CCIF stays low until the emulated EEPROM file system has created the associated EEPROM data record The CCIF flag will also clear upon execution of any CSEc command and w...

Page 721: ...no effect 0b No protection violation detected 1b Protection violation detected 3 1 Reserved 0 MGSTAT0 Memory Controller Command Completion Status Flag The MGSTAT0 status flag is set if an error is det...

Page 722: ...nd and release MCU security ERSAREQ is not directly writable but is under indirect user control Refer to the device s Chip Configuration details on how to request this command The ERSAREQ bit sets whe...

Page 723: ...EERDY EEERDY This flag indicates if the EEPROM backup data has been copied to the FlexRAM and is therefore available for read access During the reset sequence the EEERDY flag remains clear while CCIF...

Page 724: ...full erase to unsecure the part When access is granted SEC is unsecure or SEC is secure and FSLACC is granted factory testing has visibility of the current flash contents The state of the FSLACC bits...

Page 725: ...am flash memory 32 4 4 1 5 3 Diagram Bits 7 6 5 4 3 2 1 0 R OPT W Reset u u u u u u u u 32 4 4 1 5 4 Fields Field Function 7 0 OPT Nonvolatile Option These bits are loaded from flash to this register...

Page 726: ...he command completes CCIF returns to 1 No command buffering or queueing is provided the next command can be loaded only after the current command completes Some commands return information to the FCCO...

Page 727: ...words 2 bytes or aligned longwords 4 bytes 1 Refers to FCCOB register name not register address 32 4 4 1 7 Program Flash Protection Registers FPROT0 FPROT3 32 4 4 1 7 1 Offset Register Offset FPROT3...

Page 728: ...program_flash_base_address n region_size region_n_end_address program_flash_base_address n 1 region_size 1 For example if the total program flash size is 512 MB the region_size is 16 KB If the lowest...

Page 729: ...n NVM Normal mode The protection can only be increased meaning that currently unprotected memory can be protected but currently protected memory cannot be unprotected Since unprotected regions are mar...

Page 730: ...rotected memory cannot be unprotected Since unprotected regions are marked with a 1 and protected regions use a 0 only writes changing 1s to 0s are accepted This 1 to 0 transition check is performed o...

Page 731: ...the partitioned data flash memory space The granularity of data flash protection cannot be less than the data flash sector size If an unused DPROT bit is set to the protected state the Erase all Block...

Page 732: ...VIOL bit A block erase of any data flash memory block see the Erase Flash Block command description is not possible if the data flash block contains any protected region or if the FlexNVM memory has b...

Page 733: ...AC BOOT_MAC_KEY boot flavor selection is absent 0b Secure boot is not complete or secure boot failure 1b Secure boot was successful 3 BFN Secure Boot Finished The BFN bit is set by the BOOT_FAILURE or...

Page 734: ...gister Offset FERSTAT 2Eh 32 4 4 1 11 2 Function This register reports the detection of uncorrected ECC errors during read access to the FTFC module The DFDIF flag is readable and writable The unassig...

Page 735: ...Reserved 32 4 4 1 12 Flash Error Configuration Register FERCNFG 32 4 4 1 12 1 Offset Register Offset FERCNFG 2Fh 32 4 4 1 12 2 Function This register enables the force and interrupt of uncorrected ECC...

Page 736: ...ion when an uncorrectable ECC fault is detected during a valid flash read access from the platform flash controller 0b Double bit fault detect interrupt disabled 1b Double bit fault detect interrupt e...

Page 737: ...flash memory as shown in the following figure Data flash size 8 DPROT0 0x0_0000 DPROT1 DPROT2 DPROT3 DPROT5 DPROT7 DPROT6 FlexNVM Last data flash address Data flash size 8 Data flash size 8 Data flash...

Page 738: ...support the built in emulated EEPROM feature or A combination of both When using the CSEc feature set the EEE Flash configuration must be selected The user s FlexNVM configuration choice is specified...

Page 739: ...the FlexNVM block 3 FlexNVM EEPROM partition The amount of FlexNVM memory used for emulated EEPROM backup see Figure 32 6 In order to achieve specified w e cycle endurance the emulated EEPROM backup s...

Page 740: ...tor that is being erased for future use and partially erases that emulated EEPROM backup sector After a write to the FlexRAM the FlexRAM is not accessible until the FSTAT CCIF bit is set The FCNFG EEE...

Page 741: ...ally corrected and any double bit ECC errors are reflected onto FERSTAT DFDIF flag at the read access from Data Flash When the FlexNVM region is configured as Emulated EEPROM any single bit ECC errors...

Page 742: ...never enter stop mode while any FTFC command is running CCIF 0 NOTE While the MCU is in very low power modes VLPR VLPW VLPS the FTFC module does not accept flash commands 32 5 5 Functional modes of op...

Page 743: ...erase commands are executing on the program flash When configured as traditional RAM writes to the FlexRAM are allowed during data flash operations Simultaneous data flash operations and FlexRAM write...

Page 744: ...xecution if all requirements are fulfilled Before launching a command the ACCERR and FPVIOL bits in the FSTAT register must be zero and the CCIF flag must read 1 to verify that any previous command ha...

Page 745: ...est that the command was not set up with valid parameters in the FCCOB register group Program and erase commands also check the address to determine if the operation is requested to execute on protect...

Page 746: ...START CCIF 1 Read FSTAT register no yes Bit Polling for Command Completion Check Figure 32 11 Generic flash command write sequence flowchart 32 5 9 2 Flash commands The following table summarizes the...

Page 747: ...hen unprotected FlexNVM block must not be partitioned for emulated EEPROM 0x09 Erase Flash Sector Erase all bytes in a program flash or data flash sector 0x0B Program Section Program data from the Sec...

Page 748: ...U security after comparing a set of user supplied security keys to those stored in the program flash 0x49 Erase All Blocks Unsecure Erase all program flash blocks data flash blocks FlexRAM emulated EE...

Page 749: ...commands that can be executed in each flash operating mode Table 32 17 Flash commands by mode FCMD Command Unsecure Secure MEEN 10 0x00 Read 1s Block 0x01 Read 1s Section 0x02 Program Check 0x07 Prog...

Page 750: ...OK OK OK Erase Flash Sector2 OK OK OK OK Data flash Read OK OK Program Phrase OK OK OK Erase Flash Sector2 OK OK OK FlexRAM Read OK OK OK OK EE Write3 OK RAM Write4 OK OK OK OK 1 PFlash X refers to a...

Page 751: ...he user margin is a small delta to the normal read reference level User margin levels can be employed to check that flash memory contents have adequate margin for normal level read operations If unexp...

Page 752: ...ogramming of bits adding more zeros is not allowed 32 5 11 1 Read 1s Block command The Read 1s Block command checks to see if an entire program flash or data flash block has been erased to the specifi...

Page 753: ...ERR Flash address is not 128 bit aligned for interleaved flash 64 bit aligned for non interleaved flash FSTAT ACCERR Read 1s fails FSTAT MGSTAT0 32 5 11 2 Read 1s Section command The Read 1s Section c...

Page 754: ...Description 0x00 Use the normal read level for 1s 0x01 Apply the User margin to the normal read 1 level 0x02 Apply the Factory margin to the normal read 1 level Table 32 24 Read 1s Section command err...

Page 755: ...ogram Check operation will then read the specified longword and compare the actual read data to the expected data provided by the FCCOB If the comparison at margin 0 fails the MGSTAT0 bit will be set...

Page 756: ...ash memory location is not allowed Re programming of existing 0s to 0 is not allowed as this overstresses the device Table 32 28 Program Phrase Command FCCOB requirements FCCOB Number FCCOB Contents 7...

Page 757: ...rase Flash Block command The Erase Flash Block operation erases all addresses in a single program flash or data flash block Table 32 30 Erase Flash Block command FCCOB requirements FCCOB Number FCCOB...

Page 758: ...32 Erase Flash Sector command FCCOB requirements FCCOB Number FCCOB Contents 7 0 0 0x09 ERSSCR 1 Flash address 23 16 in the flash sector to be erased 2 Flash address 15 8 in the flash sector to be era...

Page 759: ...e the FTFC clears the ERSSUSP bit prior to setting CCIF When an Erase Flash Sector operation has been successfully suspended the FTFC sets CCIF and leaves the ERSSUSP bit set While CCIF is set the ERS...

Page 760: ...FCNFG ERSSUSP is set a write to the FlexRAM while FCNFG EEERDY is set clears ERSSUSP and aborts the suspended operation The FlexRAM write operation is executed by the FTFC Note Aborting the erase leav...

Page 761: ...P Execute Yes DONE No ERSSUSP 1 SaveEraseAlgo Set CCIF No Yes Start New ResumeErase No Abort User Cmd Interrupt Suspend Set SUSP ACK 1 ERSSCR Suspended Command Initiation Yes No Yes Yes ERSSCR Complet...

Page 762: ...Flash address 23 16 2 Flash address 15 8 3 Flash address 7 0 1 4 Number of double phrases for interleaved blocks phrases for non interleaved blocks to program 15 8 5 Number of double phrases for inter...

Page 763: ...s 1 If required execute the Set FlexRAM Function command to make the FlexRAM available as traditional RAM and initialize the FlexRAM to all ones 2 Launch the Erase Flash Sector command to erase the fl...

Page 764: ...o the unsecure state The security byte in the flash configuration field see Flash configuration field description remains unaffected by the Read 1s All Blocks command If the read fails i e all flash m...

Page 765: ...byte 5 value A Program Once byte 6 value B Program Once byte 7 value After clearing CCIF to launch the Read Once command an 8 byte Program Once record is read from the program flash IFR and stored in...

Page 766: ...that the selected record is erased If erased then the selected record is programmed using the values provided The Program Once command also verifies that the programmed values read back correctly The...

Page 767: ...her contents of the flash configuration field see Flash configuration field description are erased by the Erase All Blocks command If the erase verify fails the FSTAT MGSTAT0 bit is set The CCIF flag...

Page 768: ...cleared once the operation completes and the normal FSTAT error reporting except FPVIOL is available as described in Erase All Blocks command 32 5 11 12 Verify Backdoor Access Key command The Verify...

Page 769: ...has not been enabled see the description of the FSEC register FSTAT ACCERR This command is launched and the backdoor key has mismatched since the last reset FSTAT ACCERR 32 5 11 13 Erase All Blocks Un...

Page 770: ...not be launched from flash memory since flash memory resources are not accessible during Program Partition command execution Changes related to execution of the Program Partition command take effect...

Page 771: ...lots for a range of 1 to 17 User Key_ n keys For non CSEc enabled parts the key allocation must be set to Zero keys 2 b00 otherwise the command will return an error NOTE For CSEc enabled parts once Fl...

Page 772: ...e has no effect if the KEY_USAGE attribute is 0 See the CMD_LOAD_KEY command for more information on the new attribute Table 32 52 Valid emulated EEPROM data set size codes 2 KB FlexRAM configurations...

Page 773: ...2M configuration where DFlash is implemented in multiple blocks the FlexNVM may only be configured into all Data flash or 64 KB emulated EEPROM backup with the remainder left as Data Flash Thus there...

Page 774: ...R The EEPROM data size and FlexNVM partition code bytes are not initially 0xFFFF FSTAT ACCERR Invalid EEPROM Data Set Size Code is entered see Table 32 53 for valid codes FSTAT ACCERR Invalid FlexNVM...

Page 775: ...FCNFG EEERDY flags Write a background of ones to all FlexRAM locations Set the FCNFG RAMRDY flag 0xAA Complete interrupted EEPROM quick write process Clear the FCNFG EEERDY flag and FCNFG RAMRDY flag...

Page 776: ...te activity is interrupted by a reset or loss of power before finalizing the record BO detection code 0x04 will be returned If the EEPROM quick write activity is interrupted by a reset before writing...

Page 777: ...emulated EEPROM but FlexNVM is not partitioned for emulated EEPROM FSTAT ACCERR Set if FlexRAM Function Control Code is set to 0xAA 0x77 or 0x55 but FCNFG EEERDY 0 FlexRAM not in emulated EEPROM mode...

Page 778: ...flash configuration field is unprotected If the flash security byte is successfully programmed its new value takes effect after the next MCU reset 32 5 12 2 1 Un securing the MCU using backdoor key a...

Page 779: ...ing the FSEC SEC bits A successful execution of the Verify Backdoor Access Key command changes the security in the FSEC register only It does not alter the security byte or the keys stored in the Flas...

Page 780: ...cated These commands are referred to as the CSEc command set The CSEc command set requires input data and command to be entered as described in User CSEc command interface and command set NOTE 1 It is...

Page 781: ...est Also supported are the CSEc Keys as described The flash keys are stored in the EEERAM space with a configurable amount of space for flash keys The space is subtracted from the end address range of...

Page 782: ...CMD_RND to generate a random number The PRNG uses the PRNG_STATE KEY and Seed per SHE spec and the AIS20 standard as follows PRNG_STATEi ENCECB PRNG_KEY PRNG_STATE i 1 RND PRNG_STATEi 3 For additional...

Page 783: ...ey blocking erase of all keys This also results in negating the capability of Failure Analysis return is ever applicable Care must be taken if write protecting any keys is to be used in the applicatio...

Page 784: ...8 bit block sized data Cipher based Message Authentication Code CMAC generation and verification is also supported by the AES 128 engine in addition with use of Miyaguchi Prenell compression function...

Page 785: ...ich particular ERC_ codes apply to it ERC_GENERAL_ERROR Example FuncID is not valid ERC_SEQUENCE_ERROR Example CalSeq invalid continuation a command error changed command type ERC_GENERAL_ERROR Exampl...

Page 786: ...rred to from the CSEc There are two use cases One most common is a copy all data and the command function call method and the other is a pointer and function call method In the copy method the main co...

Page 787: ...x0C RND 0x0D Reserved 0x0F BOOT_OK 0x0E BOOT_FAILURE 0x10 GET_ID 0x11 BOOT_DEFINE 0x12 DBG_CHAL 0x14 Reserved 0x13 DBG_AUTH 0x15 Reserved 0x16 MP_COMPRESS 0x17 0xFF Reserved Command Header Bytes as sh...

Page 788: ...from CSEc 2 3 4 5 6 7 To setup a CSEc command the user should first enter the data as required in 128 bit blocks as many blocks as desired within the seven pages allowed at one given time Followed by...

Page 789: ...t pages are to be processed All data must be presented in 128 bit blocks all padding must be done by the application This command may also be extended by using the CallSeq field to 0x01 for continued...

Page 790: ...unction encrypts a number of PLAIN_TEXT 128 bits blocks with the key identified by the KEY_ID 5 bits and Initialization vector IV then returns CIPHER_TEXT 128 bits blocks for each input block All data...

Page 791: ...IPHER_TEXT 3 0 15 5 CIPHER_TEXT 4 0 15 6 CIPHER_TEXT 5 0 15 7 CIPHER_TEXT 6 0 15 Subsequent pages of information are provided with the Byte 2 field of the CSEc Command Header indicating an ongoing ope...

Page 792: ...mand may also be extended by using the CallSeq field to 0x01 for continued pages of data All data presented must be in 128 bit blocks any padding must be done by the application Table 32 68 Decrypt EC...

Page 793: ...ction decrypts a number of CIPHER_TEXT 128 bits blocks with the key identified by the KEY_ID 5 bits and Initialization vector IV then returns PLAIN_TEXT 128 bits blocks for each input block All data m...

Page 794: ...PLAIN_TEXT 3 0 15 5 PLAIN_TEXT 4 0 15 6 PLAIN_TEXT 5 0 15 7 PLAIN_TEXT 6 0 15 Subsequent pages of information are provided with the Byte 2 field of the CSEc Command Header indicating an ongoing operat...

Page 795: ...divide by 128 bit Output does not reflect the CMAC value until the full message has been processed at which point it overwrites the second page of data as indicated in Figure 32 30 Table 32 70 Generat...

Page 796: ...uation of input parameters 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0x05 0x00 0x01 KeyID Error Bits Reserved MESSAGE_LENGTH 1 DATA 8 0 15 2 DATA 9 0 15 3 DATA 10 0 15 4 DATA 11 0 15 5 DATA 12 0 15 6 DATA 13...

Page 797: ...rue for CMD_VERIFY_MAC pointer method If CMD_GENERATE_MAC pointer method is executed on non PFlash locations the result will be unpredictable the same is true for CMD_VERIFY_MAC pointer method Figure...

Page 798: ...writing the DATA1 block at the end of the operation with the MAC verification status The continuation examples show DATA1 10 by continuing from the first example but DATA7 would be written in place of...

Page 799: ...TA 3 0 15 4 DATA 4 0 15 5 DATA 5 0 15 6 DATA 6 0 15 7 MAC 0 15 Figure 32 35 Continuation of input parameters 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0x06 0x00 0x01 KeyID Error Bits Reserved MAC Length Reser...

Page 800: ...ts Reserved MAC Length Reserved MESSAGE_LENGTH 1 Flash Start Address Reserved 2 MAC 0 15 3 Reserved 4 5 6 7 Figure 32 38 Verify MAC pointer method output parameters 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0...

Page 801: ...d more information showing which KBS 0 or 1 is requested This will be communicated by an additional requirement of entering the KEY_ID KBS KeyIDx 3 0 Lastly the KeyIDx 3 0 in M1 must be consistent wit...

Page 802: ...VERIFY_ONLY flag for CSEc keys the FID field will be extended by one bit with the VERIFY_ONLY flag and the adjacent zero fill field is reduced by one bit to be a total of 94 bits If SFE enabled then t...

Page 803: ...lue The command header fields in Bytes 1 3 are ignored while setting Byte 2 to 0x01 will create a sequence error Table 32 74 LOAD_PLAIN_KEY command details Parameter Direction Width KEY IN 128 KEYRAM_...

Page 804: ...will become a constant 0 block Table 32 75 Export RAM_KEY command details Parameter Direction Width M1 OUT 128 M2 OUT 256 M3 OUT 128 M4 OUT 256 M5 OUT 128 K1 KDF KEYSECRET_KEY KEY_UPDATE_ENC_C K2 KDF...

Page 805: ...called before the CMD_RND command and after every power cycle or reset Bytes 1 3 of the command header are ignored Table 32 76 INIT_RNG command details Parameter Direction Width NONE The command has t...

Page 806: ...ed by CMD_INIT_RNG before the seed may be extended Table 32 77 EXTEND_SEED command details Parameter Direction Width ENTROPY IN 128 The command has to ignore active debugger protection or secure boot...

Page 807: ...28 IF SREGRND_INIT 0 PRNG_STATEi ENCECB KEY PRNG_KEY PRNG_STATEi 1 RND PRNG_STATEi END IF Error Codes ERC_NO_ERROR ERC_SEQUENCE_ERROR ERC_RNG_SEED ERC_MEMORY_FAILURE ERC_BUSY ERC_GENERAL_ERROR Figure...

Page 808: ...r the autonomous secure boot finishes per CMD_BOOT_DEFINE configuration Table 32 80 CMD_BOOT_FAILURE Command Details Parameter Direction Width NONE The command will impose the same sanctions as if CMD...

Page 809: ...alled once after ever power cycle reset and may only be called if SECURE_BOOT did not detect any errors before and if CME_BOOT_FAILIRE was not called NOTE CSEc module provides for the first autonomous...

Page 810: ...is command as the MASTER_ECU_KEY is the only valid key to be considered Table 32 84 GET_ID command details Parameter Direction Width CHALLENGE IN 128 ID OUT 120 SREG OUT 8 MAC OUT 128 ID UID MAC CMACK...

Page 811: ...of CBC encode data that is processed through continuations of inputting data through the PRAM seven block input buffer could be cancelled by giving an illegal continuation of the next segment of data...

Page 812: ...f a reset or any interruption of the part occurs between updating Code and matching SIZE BOOT_MAC with the Strict Boot option enabled the result will be mismatch of BOOT_MAC to calculated CMAC thus th...

Page 813: ...equest a random number which the user will use along with the MASTER_ECU_KEY and UID to return a authorization request using the CMD_DBG_AUTH command NOTE The CMD_DBG_CHAL command must be followed by...

Page 814: ...et on any of the keys the CMD_DEBUG does not execute the erase of any keys This also implies that the ERSALL and ERSALLU and erase all that is triggered external to the FTFC will not be able to execut...

Page 815: ...ERC_WRITE_PROTECTED ERC_RNG_SEED ERC_NO_DEBUGGING ERC_MEMORY_FAILURE ERC_BUSY ERC_GENERAL_ERROR Figure 32 52 DBG_AUTH input parameters 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0x13 0x00 0x00 KeyID Error Bits...

Page 816: ...5 6 7 8 9 A B C D E F 0 0x16 0x00 0x00 KeyID Error Bits Reserved PAGE_LEN GTH 1 DATA 1 0 15 2 DATA 2 0 15 3 DATA 3 0 15 4 DATA 4 0 15 5 DATA 5 0 15 6 DATA 6 0 15 7 DATA 7 0 15 Figure 32 54 MP compress...

Page 817: ...FOPT and FSEC registers and the FCNFG RAMRDY EEERDY bits Boot will proceed according to the configuration set by the BOOT_DEFINE command secure boot or not and what type of secure boot CCIF is cleared...

Page 818: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 818 NXP Semiconductors...

Page 819: ...vice It supports SDR and HyperRAM modes upto 4 and 8 bidirectional data lines respectively NOTE The following are not supported AHB Write Data learning feature Breakpoint and Watchpoint memory regions...

Page 820: ...ng recognition External flash acts a store for font character data RDS Radio External RAM used for temporary storage of RDS data 33 1 5 Supported read modes Read modes QuadSPI_MC R DDR_EN QuadSPI_MC R...

Page 821: ...e QuadSPI simultaneously As such the following external memory options can be supported A single Quad Flash on the A side or A single HyperRAM on the B side or A single Quad Flash on the B side Figure...

Page 822: ...SOCCFG 3 Program QuadSPI_MCR MDIS to 0 33 1 9 Clock ratio between QuadSPI clocks Below clock relationship should be maintained between SFIF_CLK flash internal reference clock and AHB read interface cl...

Page 823: ...C_DIV1 is clock source of Quadspi Internal reference Clock SCLKCFG 3 Reference clock selection for DQS for Flash B 0 Inverted Clock from SCLKCFG 2 selected as DQS 1 Clock from SCLKCFG 2 selected as DQ...

Page 824: ...performance improvement through the gasket SOCCFG 17 Burst read enable controls the bus gasket s handling of burst read transactions 0 Burst reads are converted into a series of single transactions o...

Page 825: ...nt vendors Refer Serial Flash Devices for example sequences Single dual quad and octal modes of operation Double data rate DDR Double trasfer rate DTR mode wherein the data is generated on every edge...

Page 826: ...changes and able to support all existing vendor commands and operations Software needs to select the corresponding sequence according to the connected flash device Supports all types of addressing 33...

Page 827: ...KFA PCSFA2 PCSFA1 QuadSPI Bus Flash A QuadSPI Bus Flash B define Peripheral Bus AHB Bus Addr Cmd wr_data Data rd_data Data Registers read Addr Size read_done Data DQSFA IOFB 7 0 Figure 33 2 QuadSPI Bl...

Page 828: ...le in Module Disable Mode The module enters the mode by setting QSPI_MCR MDIS or when a request is asserted by an external controller while QSPI_MCR DOZE is set 33 2 4 Acronyms and Abbreviations The f...

Page 829: ...done by the system Refer to the system address map QSPI_ARDB_BASE First address of QuadSPI Rx Buffer on system memory map Set To set a bit or bits means to establish logic level one on the bit or bits...

Page 830: ...that share IOFB PCSFB2 Peripheral Chip Select Flash B2 O This signal is the chip select for the serial flash device B2 B2 represents the second of the two flash devices that share IOFB SCKFA Serial Cl...

Page 831: ...g write data phase DQSFB Data Strobe signal Flash B I O Data strobe signal for port B Some flash vendors provide the DQS signal to which the read data is aligned in DDR mode It is also provided as an...

Page 832: ...Pad I O Instructions pad 2 b11 IOFx 7 0 Not Driven Driven for Tx Instr only Driven all the time to logic level 1 Figure 33 3 Serial Flash Access Scheme The different phases and the I O driving charact...

Page 833: ...manently throughout all the phases In Individual Flash Mode this applies to the selected flash device 33 4 Memory Map and Register Definition This section provides the memory map and register definiti...

Page 834: ...tion and 0x190 does not give transfer error QuadSPI memory map Absolute address hex Register name Width in bits Access Reset value Section page 4007_6000 Module Configuration Register QuadSPI_MCR 32 R...

Page 835: ...4007_6150 TX Buffer Status Register QuadSPI_TBSR 32 R 0000_0000h 33 4 2 18 858 4007_6154 TX Buffer Data Register QuadSPI_TBDR 32 R W 0000_0000h 33 4 2 19 858 4007_6158 Tx Buffer Control Register Quad...

Page 836: ...5 4007_6228 RX Buffer Data Register QuadSPI_RBDR10 32 R 0000_0000h 33 4 2 30 875 4007_622C RX Buffer Data Register QuadSPI_RBDR11 32 R 0000_0000h 33 4 2 30 875 4007_6230 RX Buffer Data Register QuadSP...

Page 837: ..._6300 LUT Key Register QuadSPI_LUTKEY 32 R W 5AF0_5AF0h 33 4 2 31 876 4007_6304 LUT Lock Configuration Register QuadSPI_LCKCR 32 R W 0000_0002h 33 4 2 32 876 4007_6310 Look up Table register QuadSPI_L...

Page 838: ...3 877 4007_6360 Look up Table register QuadSPI_LUT20 32 R W See section 33 4 2 33 877 4007_6364 Look up Table register QuadSPI_LUT21 32 R W See section 33 4 2 33 877 4007_6368 Look up Table register Q...

Page 839: ...7_63B8 Look up Table register QuadSPI_LUT42 32 R W See section 33 4 2 33 877 4007_63BC Look up Table register QuadSPI_LUT43 32 R W See section 33 4 2 33 877 4007_63C0 Look up Table register QuadSPI_LU...

Page 840: ...C Look up Table register QuadSPI_LUT59 32 R W See section 33 4 2 33 877 4007_6400 Look up Table register QuadSPI_LUT60 32 R W See section 33 4 2 33 877 4007_6404 Look up Table register QuadSPI_LUT61 3...

Page 841: ...SWRSTSD W CLR_TXF CLR_RXF Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Notes END_CFG field See the module configuration for the device specific reset value QuadSPI_MCR field descriptions Field Description 31 24...

Page 842: ...0 IOFA 2 is driven to logic L 1 IOFA 2 is driven to logic H 15 DOZE Doze Enable The DOZE bit provides support for externally controlled Doze Mode power saving mechanism 0 A doze request will be ignor...

Page 843: ...rom controller during Write data phase This is valid for HyperRAM where Data strobe acts as a Read Write Data Strobe RWDS For more details refer HyperRAM Support 0 DQS as an output from controller is...

Page 844: ...d to by the SEQID field Refer to Normal Mode for details about the command triggering and command execution Write QSPI_SR IP_ACC 0 Address 4007_6000h base 8h offset 4007_6008h Bit 31 30 29 28 27 26 25...

Page 845: ...DH programming options are shown below Other combinations are invalid 00 Data aligned with the posedge of Internal reference clock of QuadSPI 01 Data aligned with 2x serial flash half clock 15 12 Rese...

Page 846: ...Priority Enable When set the master associated with this buffer is assigned a priority higher than the rest of the masters An access by a high priority master will suspend any ongoing prefetch by anot...

Page 847: ...AHB triggered access to serial flash For example a value of 0x2 will set transfer size to 16 bytes When ADATSZ 0 the data size mentioned the sequence pointed to by the SEQID field overrides this value...

Page 848: ...er ID The ID of the AHB master associated with BUFFER2 Any AHB access with this master port number is routed to this buffer It must be ensured that the master IDs associated with all buffers must be d...

Page 849: ...is value Software should ensure that this transfer size is not greater than the size of this buffer 7 4 Reserved This field is reserved MSTRID Master ID The ID of the AHB master associated with BUFFER...

Page 850: ...or more information Reserved This field is reserved 33 4 2 9 SOC Configuration Register QuadSPI_SOCCR This register is programmed at chip level for QuadSPI delay chain configuration For details refer...

Page 851: ...X0 Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QuadSPI_BUF0IND field descriptions Field Description 31 3 TPINDX0 Top index of buffer 0 Reserved This field is reser...

Page 852: ...is the difference between the BUF2IND and BUF1IND The register value should be entered in bytes For example if BUF1IND 0x130 then setting BUF2IND 0x180 will set buffer2 size to 0x50 bytes It is the re...

Page 853: ...6 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SFADR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QuadSPI_SFAR field descriptions Field Description...

Page 854: ...rial flash mode 1 Word 2 byte addressable serial flash mode 15 4 Reserved This field is reserved CAS Column Address Space Defines the width of the column address If the coulmn address is say 2 0 of QS...

Page 855: ...n for SDR instructions Select the delay with respect to the reference edge for the sample point valid for full speed commands 0 One clock cycle delay 1 Two clock cycles delay 5 FSPHS Full Speed Phase...

Page 856: ...the number QSPI_RBCT WMRK 1 on RX Buffer POP event The RX Buffer can be popped using DMA or pop flag QSPI_FR RBDF The QSPI_RSER RBDDE defines which pop has to be done For further details refer to AHB...

Page 857: ...I_ARDB0 to QSPI_ARDB31 1 RX Buffer content is read using the IP Bus registers QSPI_RBDR0 to QSPI_RBDR31 7 5 Reserved This field is reserved WMRK RX Buffer Watermark This field determines when the read...

Page 858: ...d to 0 Refer to TX Buffer Data Register QuadSPI_TBDR for details 15 14 Reserved This field is reserved 13 8 TRBFL TX Buffer Fill Level The TRBFL field contains the number of entries of 4 bytes each av...

Page 859: ...er Address 4007_6000h base 158h offset 4007_6158h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved WMRK W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 860: ...r TX Buffer and the AHB Buffer Address 4007_6000h base 15Ch offset 4007_615Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Reserved Reserved TXFULL TXDMA TXWA TXEDA RXDMA Reserved RXFULL Rese...

Page 861: ...ted or running 25 TXWA TX Buffer watermark Available Asserted when the number of available spaces in TX buffer is greater than or equal to the value give by QSPI_TBCT WMRK 24 TXEDA Tx Buffer Enough Da...

Page 862: ...pty Asserted when AHB 3 buffer contains data 9 AHB2NE AHB 2 Buffer Not Empty Asserted when AHB 2 buffer contains data 8 AHB1NE AHB 1 Buffer Not Empty Asserted when AHB 1 buffer contains data 7 AHB0NE...

Page 863: ...e transaction in the serial flash device itself but only to the behavior and conditions visible in the QuadSPI module Write Enabled Mode Address 4007_6000h base 160h offset 4007_6160h Bit 31 30 29 28...

Page 864: ...ta sent to the serial flash device is all F in case of valid TX underrun Here valid underrun means that it should have occurred during the transacting such that few bytes i e less than 4 bytes are lef...

Page 865: ...response 14 AITEF AHB Illegal transaction error flag Set whenever there is no response generated from QSPI to AHB bus in case of illegal transaction and the watchdog timer expires The timer value is t...

Page 866: ...ster QuadSPI_RSER The QuadSPI_RSER register provides enables and selectors for the interrupts in the QuadSPI module NOTE Each flag of the QuadSPI_FR register enabled as source for an interrupt prevent...

Page 867: ...adSPI_SR TXWA status bit is set NOTE Once set writting a zero does not impact DMA transfers even though the bit gets written a zero After QuadSPI_MCR SWRSTHD is used to do software reset for AHB Domai...

Page 868: ...t enable 0 No AITEF interrupt will be generated 1 AITEF interrupt will be generated 13 AIBSIE AHB Illegal Burst Size Interrupt Enable 0 No AIBSEF interrupt will be generated 1 AIBSEF interrupt will be...

Page 869: ...escription 0 TFIE Transaction Finished Interrupt Enable 0 No TFF interrupt will be generated 1 TFF interrupt will be generated Chapter 33 Quad Serial Peripheral Interface QuadSPI MWCT101xS Series Refe...

Page 870: ...uspended when a high priority AHB master makes an access before the AHB sequence completes the data transfer requested Address 4007_6000h base 168h offset 4007_6168h Bit 31 30 29 28 27 26 25 24 23 22...

Page 871: ...left to be read in the suspended sequence Valid only when SUSPND is set to 1 b1 Value in terms of 64 bits or 8 bytes 8 Reserved This field is reserved 7 6 SPDBUF Suspended Buffer Provides the suspende...

Page 872: ...et 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved 0 Reserved 0 W IPPTRC BFPTRC Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QuadSPI_SPTRCLR field descriptions Field Desc...

Page 873: ...TPADA1 Top address for Serial Flash A1 In effect TPADxx is the first location of the next memory Reserved This field is reserved 33 4 2 27 Serial Flash A2 Top Address QuadSPI_SFA2AD The QSPI_SFA2AD r...

Page 874: ...19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TPADB1 Reserved W Reset 0 0 0 0 0 0 0 0 0 0 Notes TPADB1 field See the module configuration for the device specific reset values QuadSPI_SFB1AD fiel...

Page 875: ...he number of valid buffer entries available in the RX Buffer Example 1 RX Buffer filled completely with 32 words In this case the address range for valid read access extends from QuadSPI_RBDR0 to Quad...

Page 876: ...egister QuadSPI_LCKCR The LUT lock configuration register is used along with QSPI_LUTKEY register to lock or unlock the LUT This register has to be written immediately after QSPI_LUTKEY register for t...

Page 877: ...ences to generate a valid serial flash transaction There are a total of 64 LUT registers These 64 registers are divided into groups of 4 registers that make a valid sequence Therefore QSPI_LUT 0 QSPI_...

Page 878: ...s valid for both IP and AHB commands Table 33 8 Serial Flash Address Assignment Parameter Function Access Mode QSPI_AMBA_BASE 31 10 22 bits QuadSPI AHB base address TOP_ADDR_MEMA1 T PADA1 Top address...

Page 879: ...ed Serial Flash Data Individual Flash Mode on Flash A for details and to Table 33 16 and Table 33 17 for information about the byte ordering Memory Mapped Serial Flash Data Individual Flash Mode on Fl...

Page 880: ...d are NONSEQ and BUSY AHB access type SEQ is treated in the same way like NONSEQ Refer to the AMBA AHB Specification for further details 33 5 2 Memory Mapped Serial Flash Data Individual Flash Mode on...

Page 881: ...al Flash Data Individual Flash Mode on Flash B Starting with address TOP_ADDR_MEMA2 the content of the first external serial flash devices is mapped into the address space of the device containing the...

Page 882: ...l flash provides undefined results For details concerning the read process refer to Flash Read 33 5 4 AHB RX Data Buffer QSPI_ARDB0 to QSPI_ARDB31 NOTE See the System Memory map in this document for t...

Page 883: ...ata Buffer register ARDB23 32 R W 0000_0000h 33 5 4 1 882 60 AHB RX Data Buffer register ARDB24 32 R W 0000_0000h 33 5 4 1 882 64 AHB RX Data Buffer register ARDB25 32 R W 0000_0000h 33 5 4 1 882 68 A...

Page 884: ...ield Description ARXD ARDB provided RX Buffer Data Byte order endianness is identical to the RX Buffer Data Registers 33 6 Interrupt Signals The interrupt request lines of the QuadSPI module are mappe...

Page 885: ...n Port A and Port B Individual Flash Mode Access to Flash A Yes N a Yes Individual Flash Mode Access to Flash B N a Yes Yes Note If two different flash devices are attached they can be operated only i...

Page 886: ...CAS into consideration DUMMY 6 d3 Number of dummy clock cycles should be 64 cycles Provide the serial flash with dummy cycles as per the operand The PAD information defines the number of pads in inpu...

Page 887: ...bytes Read data from flash on the number of pads specified at each clock edge of serial flash The data size may be overwritten by writing to the ADATSZ field of the QSPI_BUFxCR registers for AHB init...

Page 888: ...rial flash is buffered in flexible AHB buffers There are four such flexible buffers The size of each of these buffers is configurable with the minimum size being 0 Bytes and maximum size being the siz...

Page 889: ...2 buffer1 buffer0 QSPI_BFGENCR SEQID LUT Figure 33 4 Flexible AHB Buffers Buffer0 may optionally be configured to be associated with a high priority master by setting the QSPU_BUF0CR HP_EN bit An acce...

Page 890: ...roller supports HBURST and HSIZE on the AHB interface HBURST indicates if the transfer forms part of a burst Four eight and sixteen beat bursts are supported and the burst may be either incrementing o...

Page 891: ...33 5 QuadSPI HBURST support NOTE The software must take care that the prefetch size should never be set less than the minimum data needed by any external interface to start processing NOTE Whenever a...

Page 892: ...ed again The key for locking or unlocking the LUT is 0x5AF05AF0 The process for locking and un locking the LUT is as follows Locking the LUT 1 Write the key 0x5AF05AF0 in to the LUT Key Register QuadS...

Page 893: ...rts and the status bit QSPI_SR BUSY is set 3 Communication with the external serial flash device is started and the transaction is executed 4 When the transaction is finished all transmit and receive...

Page 894: ...scribed in Memory Mapped Serial Flash Data Individual Flash Mode on Flash A and Memory Mapped Serial Flash Data Individual Flash Mode on Flash B 33 7 2 7 Flash Programming In all cases the memory sect...

Page 895: ...ongoing It is up to the user to monitor the relevant status information available from the serial flash device and to ensure that the programming is finished properly 33 7 2 8 Flash Read Host access t...

Page 896: ...uration register QSPI_BFGENCR It is the responsibility of the software to ensure that a correct read sequence in programmed in the LUT in accordance with the serial flash device connected on board Fla...

Page 897: ...ffer section for details AHB Buffer Byte Swapper for endianness Note READ ACCESS READ ACCESS WRITE ACCESS System AHB IPS External Flash QuadSPI Figure 33 7 QuadSPI memory map The RX Buffer is implemen...

Page 898: ...on must ensure that the DMA controller of the related device is programmed appropriately like it is described in DMA Usage DMA controlled read out is triggered fully automatically by the assertion of...

Page 899: ...R SFADR field corresponds to bit position QSPI_RBDR0 31 24 register for IP Command read In contrast to that for AHB Command read the bytes are always positioned according to the byte ordering of the A...

Page 900: ...module has different flags that can only generate interrupt requests and one flag that can generate interrupt as well as DMA requests The following table lists the eight conditions Note that the flag...

Page 901: ...ve Buffer Drain IRQ derived from the QSPI_FR RBDF flag indicates that the RX Buffer of the QuadSPI module has data available from the serial flash device to be read by the host It remains set as long...

Page 902: ...ired to provide at least four entry in the TX Buffer prior to starting the execution of the page programming command The application must ensure that the required number of data bytes is written into...

Page 903: ...be programmed with 8 d32 as the operand value with QSPI_SFACR CAS programmed to 0 If a flash needs some bits of the address as its column address then it must always considered that the total bits req...

Page 904: ...mmand accordingly It must be ensured that the total number of address bits request by flash as its page and column address must not be more than 32 bits Word addressable mode for Flash This mode has b...

Page 905: ...alization and application information of the QuadSPI module 33 8 1 Power Up and Reset Note that the serial flash devices connected to the QuadSPI module may require special voltage characteristics of...

Page 906: ...SR AHBACC and the QSPI_SR BUSY bits are asserted simultaneously immediately after the execution is started When the instruction on the serial flash device has been finished these bits are de asserted...

Page 907: ...countered by the controller in any of the sequences Command Arbitration Error IPIEF TFF not asserted in conjunction with that command IP Command Error caused when IP access is currently in progress IP...

Page 908: ...specific to the DMA usage related to the QuadSPI module are given 33 8 4 1 DMA Usage in Normal Mode 33 8 4 1 1 Bandwidth considerations Careful consideration of the throughput rate of the entire chai...

Page 909: ...6 BUS cycles with one additional CPU access to QuadSPI costing 2 BUS clock cycles Total 6 8 3 2 2 32 4 2 30 BUS clock cycles Table 33 21 Access Duration Examples Bus Clock Side QSPI_TBCT WMRK Number o...

Page 910: ...igure represents ideal scenario actual performance will depend on how the system is integrated A complementary example would be when the watermark is set to be too high In such a case the time taken b...

Page 911: ...flash mode Overhead due to clock domain crossing 1 cycle The following table lists the number of clock cycles required to read the data from the serial flash corresponding to the different settings of...

Page 912: ...via the TX buffer The table QSPI_MCR END_CFG below shows the complete bit ordering BE signifies Big Endian which means the high order bits of the associated data vectors are associated with low order...

Page 913: ...33 28 Example of QuadSPI TX Buffer TX Buffer Entry Content 0 32 h01_02_03_04 1 32 h05_06_07_08 Programming the TX Buffer into the external serial flash device results in the following byte order to be...

Page 914: ...ce at the QuadSPI module boundary 1a 32 Bit Access Read QSPI_ARDB0 0x01_02_03_04 2a 32 Bit Access Read QSPI_ARDB1 0x05_06_07_08 1b 2b 64 Bit Access Read QSPI_ARDB0 0x01_02_03_04_05_06_07_08 33 9 3 Rea...

Page 915: ...to the logic state given by the configuration bits QSPI_MCR ISD3FA QSPI_MCR ISD2FA QSPI_MCR ISD3FB and QSPI_MCR ISD2FB These outputs are driven all the time to the logic level programmed in the QSPI_...

Page 916: ...HyperRAM of the QuadSPI module Table 33 32 Read Command Spansion Hyperflash HyperRAM INSTR PAD OPERAND COMMENT CMD_DDR 0x3 0xA0 Read command with continuous burst type ADDR_DDR 0x3 0x18 24 bit row add...

Page 917: ...R_DDR 0x3 0x18 24 bit row address CADDR_DDR 0x3 0x10 16 bit column address with lower 3 bits valid rest 0 DUMMY 0x3 0x0F 15 dummy cycles READ_DDR 0x3 0x4 32 bit data read on 8 pads STOP 0x3 0x00 STOP...

Page 918: ...rite data to be sent to flash as pre command CMD_DDR Program setup phase third chip select phase 0x3 0x00 Write command with wrapped burst type CMD_DDR 0x3 0x00 8 bit address 00h treated as command CM...

Page 919: ...acronix The following table shows the Fast Dual I O DT read sequence for Macronix flashes Table 33 36 Fast Dual I O DT Read sequence Instruction Pad Operand Comment CMD 0x0 0xBD Fast Dual I O DT read...

Page 920: ...pads MODE 0x2 0xA5 2 mode cycles DUMMY 0x0 0x04 4 Dummy cycles READ 0x2 0x04 Read 32 Bits on 4 pads JMP_ON_CS 0x0 0x01 Jump to instruction 1 ADDR When in XIP mode the software should ensure that all...

Page 921: ...Numonyx Winbond flashes Table 33 41 Read Status Register Sequence Instruction Pad Operand Comment CMD 0x0 0x05 Read status register command 0x05 READ 0x0 0x01 Read status register data STOP 0x0 0x00 S...

Page 922: ...from the device containing the QuadSPI module to the external serial flash device 3 Clock to data out delay of the external serial flash device including input and output delays 4 Wire delay of appli...

Page 923: ...e clock for sampling the input data in SDR mode internal reference for serial flash data sampling internal ref clock SCK serial flash clock serial flash data tDel total Possible Sampling Points N 1 N...

Page 924: ...ing rise and fall times and timing uncertainties Depending on the timing uncertainties it may turn out in actual applications that only one possible sample position remains This is subject to careful...

Page 925: ...Data sampling in DDR mode can be supported using DQS method Refer to Data Strobe DQS sampling method for more details 33 12 3 Data Strobe DQS sampling method 33 12 3 1 Basic Description In DQS mode th...

Page 926: ...uadSPI internally samples the incoming data on both the edges of the strobe signal Refer to the figure below for more detail Internal Ref clock SCK Data Strobe Signal Data internal reference for seria...

Page 927: ...serial flash memories supporting DQS the data strobe signal is an output from the flash device that indicates when data is being transferred from the flash to the host controller The data is then cap...

Page 928: ...t hold time requirement of flash QuadSPI internally delays the data sent to flash so that it will be easy to meet the hold requirement The QSPI_FLSHCR TDH is used for this purpose If QSPI_FLSHCR TDH i...

Page 929: ...table compares the various power modes available For Run and Very Low Power Run VLPR modes there are corresponding Stop modes Stop modes VLPS STOP1 STOP2 are similar to Arm sleep deep mode VLPR opera...

Page 930: ...y flash memory access mode 1 MHz LVD off SIRC provides a low power 4 MHz source for the core the bus and the peripheral clocks Run Very Low Power Stop VLPS via WFI instruction Places the chip in a sta...

Page 931: ...RL for more details When configured for STOP1 the core clocks system clocks and bus clocks are all gated When configured for STOP2 only the core and system clocks are gated but the bus clock remains a...

Page 932: ...and negate Stop mode signals to all bus masters and slaves software must ensure that bus masters and slaves that are not involved with the DMA wake up and transfer remain in a known state This can be...

Page 933: ...es NOTE Do not enter any stop mode without first exiting CPO Before entering to CPO mode software should make sure that all ongoing communication should be completed Because CPO reuses stop mode logic...

Page 934: ...us error The DMA wake up is also supported during CPO and causes CPOACK status to clear and the AIPS peripheral space to be accessible for the duration of the DMA wake up After the DMA wake up complet...

Page 935: ...enabled The VLPR modes offer a lower power operating mode than normal modes VLPR is limited in frequency STOP1 STOP2 RUN VLPS VLPR Any RESET HSRUN 5 1 2 4 3 Figure 34 1 Power mode state transition dia...

Page 936: ...he targeted low power mode When all acknowledges are detected system clock bus clock and flash memory clock are turned off simultaneously 3 The SCG and Mode Controller shut off clock sources and or th...

Page 937: ...chip Table 34 4 Module operation in available power modes Modules VLPR1 STOP STOP1 STOP2 VLPS1 RUN HSRUN Core Modules NVIC FF Off Off FF FF System Modules System Mode Controller Power Mangement Contr...

Page 938: ...48 MHz max FIRC as a source 40 MHz max PLL as a source 56 MHz max PLL as a source Memory and memory interfaces Flash memory Only read operation can be done 1 MHz max No FTFC commands of any type incl...

Page 939: ...sync operation FF FF LPI2C FF only SIRC as a source Async operation in STOP1 FF in STOP2 Async operation FF FF FlexIO FF only SIRC as a source Async operation in STOP1 FF in STOP2 OFF FF FF CAN FF onl...

Page 940: ...pin or external pin to DAC compares Windowed sampled filtered modes of operation are not available while in stop or VLPS modes 4 Device can support ASYNC wakeup from VLPS through GPIO Refer to table...

Page 941: ...ch mode and the functionality available while in each of the modes The SMC is able to function during even the deepest low power modes See AN4503 Power Management for Kinetis MCUs for further details...

Page 942: ...configure the various modes of operation for the device The following table describes the power modes available for the device Table 35 1 Power modes Mode Description RUN The MCU can be run at full s...

Page 943: ...not being entered correctly SMC memory map Absolute address hex Register name Width in bits Access Reset value Section page 4007_E000 SMC Version ID Register SMC_VERID 32 R 0100_0000h 35 3 1 943 4007_...

Page 944: ...ion Number This read only field returns the feature set number 0x0000 Standard features implemented 35 3 2 SMC Parameter Register SMC_PARAM Address 4007_E000h base 4h offset 4007_E004h Bit 31 30 29 28...

Page 945: ...e 1 The feature is available 2 1 Reserved This field is reserved This read only field is reserved and always has the value 0 0 EHSRUN Existence of HSRUN feature This static bit states whether or not t...

Page 946: ...to enter High Speed Run mode HSRUN 0 HSRUN is not allowed 1 HSRUN is allowed 6 Reserved This field is reserved This read only field is reserved and always has the value 0 5 AVLP Allow Very Low Power...

Page 947: ...MPROT register NOTE This register is reset on Chip POR and by reset types that trigger Chip POR It is unaffected by reset types that do not trigger Chip POR See the Reset section details for more info...

Page 948: ...has the value 0 3 VLPSA Very Low Power Stop Aborted When set this read only status bit indicates an interrupt occured during the previous stop mode entry sequence preventing the system from entering t...

Page 949: ...R 0 STOPO 0 0 Reserved 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 SMC_STOPCTRL field descriptions Field Description 31 8 Reserved This field is reserved This read only field is reserved and always has...

Page 950: ...s reset on Chip POR and by reset types that trigger Chip POR It is unaffected by reset types that do not trigger Chip POR See the Reset section details for more information When in any mode any reset...

Page 951: ...0010_0000 Reserved 0100_0000 Reserved 1000_0000 Current power mode is HSRUN 35 4 Functional description 35 4 1 Power mode transitions The following figure shows the power mode state transitions availa...

Page 952: ...PR Interrupt NOTE If VLPS was entered directly from RUN transition 4 hardware forces exit back to RUN and does not allow a transition to VLPR 4 RUN VLPS PMPROT AVLP 1 PMCTRL STOPM 010 Sleep now or sle...

Page 953: ...owing sequence occurs 1 The CPU clock is gated off immediately 2 Requests are made to all non CPU bus masters to enter Stop mode 3 After all masters have acknowledged they are ready to enter Stop mode...

Page 954: ...y entering the stop mode An aborted entry is possible only if the interrupt occurs before the PMC begins the transition to stop mode regulation After this point the interrupt is ignored until the PMC...

Page 955: ...N Very Low Power Run VLPR High Speed Run HSRUN 35 4 3 1 RUN mode This is the normal operating mode for the device This mode is selected after any reset When the Arm processor exits reset it sets up th...

Page 956: ...egisters Module clock enables in the PCC can be set but not cleared To reenter Normal Run mode clear PMCTRL RUNM PMSTAT is a read only status register that can be used to determine when the system has...

Page 957: ...MCTRL RUNM to enter HSRUN Before increasing clock frequencies the PMSTAT register should be polled to determine when the system has completed entry into HSRUN mode To reenter normal RUN mode clear PMC...

Page 958: ...rectly from RUN mode exit to VLPR is disabled by hardware and the system will always exit back to RUN In VLPS the on chip voltage regulator remains in its stop regulation state as in VLPR A module cap...

Page 959: ...core clock are disabled the debug module has access to core registers and access to the on chip peripherals is blocked Chapter 35 System Mode Controller SMC MWCT101xS Series Reference Manual Rev 3 07...

Page 960: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 960 NXP Semiconductors...

Page 961: ...Datasheet for LVD LVW and LVR threshold levels 36 2 Introduction The PMC contains the internal voltage regulator power on reset POR and the low voltage detect LVD system 36 3 Features The PMC features...

Page 962: ...system The low voltage detect flag LVDF operates in a level sensitive manner The LVDF bit is set when the supply voltage falls below the trip point VLVD The LVDF bit is cleared by writing one to the...

Page 963: ...eration LVDIE set PMC_LVDSC1 LVDF is set and an LVD interrupt request occurs upon detection of a low voltage condition The LVDF bit is cleared by writing one to the PMC_LVDSC1 LVDACK bit when the supp...

Page 964: ...RW Table 36 1h Low Voltage Detect Status and Control 2 Register LVDSC2 8 RW 00h 2h Regulator Status and Control Register REGSC 8 RW Table 36 4h Low Power Oscillator Trim Register LPOTRIM 8 RW Table 36...

Page 965: ...ar LVDF Read always return 0 5 LVDIE Low Voltage Detect Interrupt Enable This bit enables hardware interrupt requests for LVDF 0b Hardware interrupt disabled use polling 1b Request a hardware interrup...

Page 966: ...ltage detect event The threshold voltage is VLVW 0b Low voltage warning event not detected 1b Low voltage warning event detected 6 LVWACK Low Voltage Warning Acknowledge This write only bit is used to...

Page 967: ...enabled 1b Low power oscillator disabled 6 LPOSTAT LPO Status Bit This bit shows the status of the LPO clock to be either in high phase logic 1 or low phase logic 0 of the clock period Software can p...

Page 968: ...ct This is useful to further reduce MCU power consumption in low power mode This bit must be set to 1 when using VLP modes 0b Biasing disabled core logic can run in full performance 1b Biasing enabled...

Page 969: ...1 0 R 0 LPOTRIM W Reset 0 0 0 u1 u u u u 1 Automatically loaded from flash memory IFR after any reset 36 6 1 5 4 Fields Field Function 7 5 Reserved 4 0 LPOTRIM LPO trimming bits These bits are used fo...

Page 970: ...Memory Map and Register Definition MWCT101xS Series Reference Manual Rev 3 07 2019 970 NXP Semiconductors...

Page 971: ...exact ADC channel number present on the device is different with packages as indicated in following table For details regarding a specific ADC channel available on a particular package see Introductio...

Page 972: ...ply monitoring purposes refer to section ADC internal supply monitoring Note that ADCx ADy and ADCx_SEy both refer to Channel y of ADCx Table 37 3 Internal channel availability ADC internal channel AD...

Page 973: ...UX will provide user a more flexible DMA triggering scheme using software based on different application requirements for example the DMA can be triggered after multiple ADC conversion completion inst...

Page 974: ...ing ADC0_SC1n ADCH as 010101b Please refer to SIM_CHIPCTL ADC_SUPPLY and SIM_CHIPCTL ADC_SUPPLYEN bits 37 6 ADC Reference Options The ADC supports the following references VREFH VREFL connected as the...

Page 975: ...tware must determine relative priority Starts conversion after a single ongoing conversion complete CMP out LPIT RTC and LPTMR are capable of triggering each ADC via TRGMUX See TRGMUX module interconn...

Page 976: ...UX_ADC0 63 1 0 Pretriggers 3 0 Triggers 3 0 in36 in34 in 31 30 Ch0 trigger Trigger_in0 Ch1 pretriggers 7 0 Pulse out trigger ACK 15 8 Ch1 trigger PDB0 Ch0 pretriggers 3 0 PDB pretriggers 3 0 TRGMUX pr...

Page 977: ...SIM_ADCOPT ADCxTRGSEL 0 PDB0 channel 0 is selected as the ADC trigger source PDB0 pre triggers will connect directly to the ADC0 ADHWTS port to control the channels The ADC0 COCO signals are fed dire...

Page 978: ...rigger0 pre trigger3 the other pre triggers cannot be used with TRGMUX ADC COCO is not required in this case Software must accommodate the intermission time between each ADC conversion Using TRGMUX al...

Page 979: ...ion The four lower triggers have the capability to be latched Irrespective of which source combination is selected the trigger requests from that source are latched and processed Latched trigger reque...

Page 980: ...f trigger handler poll the status of ADC_SC2 TRGSTLAT for all 0 c Reselect the trigger source for the trigger handler block configuration for this resides in a separate module on the chip see the chip...

Page 981: ...TRG should not be done while PDB triggering through the trigger handler as the PDB works in a closed loop with the COCO flag from the ADC and provides one trigger at a time Clearing the latched status...

Page 982: ...version invalid for second ADC results are valid due to trigger latching gasket for both conversions 4 Pretrigger delay configured greater than ADC conversion time t ADC conversion time ADC results ar...

Page 983: ...g on channel number 4 onwards through same PDB channel Sequence error for second conversion COCO might be received or might not Both the conversion results are invalid Figure 37 6 Chapter 37 ADC Confi...

Page 984: ...e invalid Figure 37 7 c Triggering on channels 0 3 through trigger latching gasket Sequence error for second conversion is reported COCO will be received for both channels Both the conversion results...

Page 985: ...gering on channel number 4 onwards through same PDB channel Sequence error for second conversion COCO will not be received First conversion results are valid and second conversion results are invalid...

Page 986: ...lts are invalid Figure 37 10 c Triggering on channels 0 3 through trigger latching gasket Sequence error for second conversion is reported COCO will be received for both channels Both the conversion r...

Page 987: ...nfigured is greater than ADC conversion time No sequence error Both COCOs received Both conversions are valid Figure 37 12 Chapter 37 ADC Configuration MWCT101xS Series Reference Manual Rev 3 07 2019...

Page 988: ...DC When a PDB pre trigger and trigger output starts an ADC conversion an internal lock associated with the corresponding pre trigger is activated This lock becomes inactive when receiving the COCO sig...

Page 989: ...trigger1 ADHWTS B PDB_ch0_pretrigger0 ADHWTS A PDB_trigger_in0 FTM_init_trig PWM PDB_ch0_pretrigger3 ADHWTS D ADHWT Figure 37 14 Example PWM Load Diagnosis ADC Trigger Concept 1 Timing Chapter 37 ADC...

Page 990: ...r ADC ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ADC ch8 ch9 ch10 ch11 ch12 ch13 ch14 ch15 ISR2 ISR1 Figure 37 15 Example PWM Load Diagnosis ADC Trigger Concept 2 Timing 37 13 ADC calibration scheme After a POR...

Page 991: ...upon subsequent exits from power mode STOP2 re calibration is not required Since the power is continuous in all of the device power modes STOP2 RUN and HSRUN all of the ADC specifications are maintain...

Page 992: ...ADC calibration scheme MWCT101xS Series Reference Manual Rev 3 07 2019 992 NXP Semiconductors...

Page 993: ...cessive approximation algorithm with up to 12 bit resolution Up to 32 single ended external analog inputs Single ended 12 bit 10 bit and 8 bit output modes Output in right justified unsigned format fo...

Page 994: ...LTCLK4 ALTCLK1 AD C K M O D E transfer C V2 CV1 CV2 Interrupt 1 AD VIN AC FE 1 SC2 Rn RA CFG1 2 Compare true Conversion trigger control MCU STOP ADHWT AD0 ADn V REFH VALTH AIEN C O C O trig g e r CLPx...

Page 995: ...he ADC analog portion uses VDDA as its power connection In some packages VDDA is connected internally to VDD If externally available connect the VDDA pin to the same voltage potential as VDD External...

Page 996: ...ntial as VDDA or may be driven by an external source to a level between the minimum VREFH and the VDDA potential VREFH must never exceed VDDA Connect the ground references to the same voltage potentia...

Page 997: ...ble 38 2 CCh ADC Plus Side General Calibration Value Register 9 CLP9 32 RW Table 38 2 D0h ADC General Calibration Offset Value Register S CLPS_OFS 32 RW 0000_0000h D4h ADC Plus Side General Calibratio...

Page 998: ...00h 1D0h ADC Data Result Registers RS 32 RO 0000_0000h 1D4h ADC Data Result Registers RT 32 RO 0000_0000h 1D8h ADC Data Result Registers RU 32 RO 0000_0000h 1DCh ADC Data Result Registers RV 32 RO 000...

Page 999: ...ADCH other than all 1s module disabled Writing any of the SC1n registers while that specific SC1n register is actively controlling a conversion aborts the current conversion None of the SC1B SC1n reg...

Page 1000: ...e actual ADC channel assignments for your device see the chip specific information The successive approximation converter subsystem is turned off when the channel bits are all set i e ADCH set to all...

Page 1001: ...ernal channel 20 is selected as input 100101b External channel 21 is selected as input 100110b External channel 22 is selected as input 100111b External channel 23 is selected as input 101000b Externa...

Page 1002: ...Trigger in Trigger Handler Block Writing a 1 to this field clears all the latched triggers inside the trigger handler except the one under processing Writing 0 has no effect This is a write only one...

Page 1003: ...00b 8 bit conversion 01b 12 bit conversion 10b 10 bit conversion 11b Reserved 1 0 ADICLK Input Clock Select Selects the input clock source to generate the internal clock ADCK See the clock distributio...

Page 1004: ...en to this register field is the desired sample time minus 1 A sample time of 1 is not supported Allows higher impedance inputs to be accurately sampled or conversion speed to be maximized for lower i...

Page 1005: ...Conversion mode D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Format 12 bit single ended D Unsigned right justified 10 bit single ended 0 D 8 bit single ended 0 D D Data The data result registers are read onl...

Page 1006: ...ed in the same way as the Rn registers Therefore the compare function uses only the CVn fields that are related to the ADC mode of operation CV2 is used only when the compare range function is enabled...

Page 1007: ...select compare function and voltage reference select of the ADC module 38 4 7 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 TRGSTERR 0 TRGSTLAT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1008: ...ed in Field not supported in ADC0_SC2 ADC1_SC2 0000b No error has occurred 0001b An error has occurred 23 20 Reserved 19 16 TRGSTLAT Trigger Status Each of these status bits indicate that a multiplexe...

Page 1009: ...trigger When hardware trigger is selected a conversion is initiated following the assertion of the ADHWT input after a pulse of the ADHWTSn input 0b Software trigger selected 1b Hardware trigger sele...

Page 1010: ...eserved 11b Reserved 38 4 8 Status and Control Register 3 SC3 38 4 8 1 Offset Register Offset SC3 94h 38 4 8 2 Function The Status and Control Register 3 SC3 controls the calibration continuous conver...

Page 1011: ...ADCO Continuous Conversion Enable Enables continuous conversions 0b One conversion will be performed or one set of conversions if AVGE is set after a conversion is initiated 1b Continuous conversions...

Page 1012: ...18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 BA_OFS W Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 38 4 9 4 Fields Field Function 31 8 Reserved 7 0 BA_O...

Page 1013: ...nt mode of operation NOTE If offset register is set to a negative value and it is lower than or equal to 0xFFF8 the ADC will not result code 0 If offset register is set to a negative value and it is l...

Page 1014: ...n result error correction algorithm 38 4 11 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 US...

Page 1015: ...algorithm 38 4 12 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 XOFS W Reset 0 0 0 0 0 0 0 0...

Page 1016: ...rection algorithm 38 4 13 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 YOFS W Reset 0 0 0 0...

Page 1017: ...calibration algorithm 38 4 14 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 G W Reset 0 0 0...

Page 1018: ...t be written before calibrating the ADC 38 4 15 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R...

Page 1019: ...sequence is done that is CAL is cleared If these registers are written by the user after calibration the linearity error specifications may not be met 38 4 16 3 Diagram Bits 31 30 29 28 27 26 25 24 2...

Page 1020: ...27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CLP3 W Reset 0 0 0 0 0 0 u1 u u u u u u u u u 1 Reset values are loaded...

Page 1021: ...0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CLP2 W Reset 0 0 0 0 0 0 u1 u u u u u u u u u 1 Reset values are loaded out of IFR 38 4 18 3 Fields Field Function 31 10 Reserved 9 0 CL...

Page 1022: ...7 6 5 4 3 2 1 0 R 0 CLP1 W Reset 0 0 0 0 0 0 0 u1 u u u u u u u u 1 Reset values are loaded out of IFR 38 4 19 3 Fields Field Function 31 9 Reserved 8 0 CLP1 CLP1 Calibration Value 38 4 20 ADC Plus Si...

Page 1023: ...et 0 0 0 0 0 0 0 0 u1 u u u u u u u 1 Reset values are loaded out of IFR 38 4 20 3 Fields Field Function 31 8 Reserved 7 0 CLP0 CLP0 Calibration Value 38 4 21 ADC Plus Side General Calibration Value R...

Page 1024: ...PX W Reset 0 0 0 0 0 0 0 0 0 u1 u u u u u u 1 Reset values are loaded out of IFR 38 4 21 3 Fields Field Function 31 8 Reserved 7 Reserved 6 0 CLPX CLPX Calibration Value 38 4 22 ADC Plus Side General...

Page 1025: ...0 0 0 0 u1 u u u u u u 1 Reset values are loaded out of IFR 38 4 22 3 Fields Field Function 31 8 Reserved 7 Reserved 6 0 CLP9 CLP9 Calibration Value 38 4 23 ADC General Calibration Offset Value Regist...

Page 1026: ...OFS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 4 23 4 Fields Field Function 31 4 Reserved 3 0 CLPS_OFS CLPS Offset Capacitor offset correction value 38 4 24 ADC Plus Side General Calibration Offset Va...

Page 1027: ...et 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 4 24 3 Fields Field Function 31 4 Reserved 3 0 CLP3_OFS CLP3 Offset Capacitor offset correction value 38 4 25 ADC Plus Side General Calibration Offset Value Regis...

Page 1028: ...OFS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 4 25 3 Fields Field Function 31 4 Reserved 3 0 CLP2_OFS CLP2 Offset Capacitor offset correction value 38 4 26 ADC Plus Side General Calibration Offset Va...

Page 1029: ...et 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 4 26 3 Fields Field Function 31 4 Reserved 3 0 CLP1_OFS CLP1 Offset Capacitor offset correction value 38 4 27 ADC Plus Side General Calibration Offset Value Regis...

Page 1030: ...OFS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 4 27 3 Fields Field Function 31 4 Reserved 3 0 CLP0_OFS CLP0 Offset Capacitor offset correction value 38 4 28 ADC Plus Side General Calibration Offset Va...

Page 1031: ...t 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 38 4 28 3 Fields Field Function 31 12 Reserved 11 0 CLPX_OFS CLPX Offset Capacitor offset correction value 38 4 29 ADC Plus Side General Calibration Offset Value Regi...

Page 1032: ...9 3 Fields Field Function 31 12 Reserved 11 0 CLP9_OFS CLP9 Offset Capacitor offset correction value 38 4 30 ADC Status and Control Register 1 SC1AA SC1Z 38 4 30 1 Offset Register Offset SC1Q 148h SC1...

Page 1033: ...hen SC2 ADTRG 0 writes to SC1A initiate a new conversion This is valid for all values of SC1A ADCH other than all 1s module disabled Writing any of the SC1n registers while that specific SC1n register...

Page 1034: ...nal channel 15 is selected as input 010000b Reserved 010001b Reserved 010010b Reserved 010011b Reserved 010100b Reserved 010101b Internal channel 0 is selected as input 010110b Internal channel 1 is s...

Page 1035: ...00b Reserved 110101b Reserved 110110b Reserved 110111b Reserved 111000b Reserved 111001b Reserved 111010b Reserved 111011b Reserved 111100b Reserved 111101b Reserved 111110b Reserved 111111b Module is...

Page 1036: ...ription Conversion mode D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Format 12 bit single ended D Unsigned right justified 10 bit single ended 0 D 8 bit single ended 0 D D Data The data result registers are...

Page 1037: ...conversion complete interrupt has been enabled or when SC1n AIEN 1 The ADC module has the capability of automatically comparing the result of a conversion with the contents of the CV1 and CV2 registe...

Page 1038: ...d using SC2 REFSEL The alternate VALTH voltage reference may select additional external pin or internal source depending on MCU configuration See the chip configuration information for the voltage ref...

Page 1039: ...d that is SC1n COCO is then set and an interrupt is generated if the respective conversion complete interrupt has been enabled that is SC1 AIEN 1 38 5 4 Conversion control Conversion mode is selected...

Page 1040: ...conversion until the correct number of conversions are completed In software triggered operation conversions begin after SC1A is written In hardware triggered operation conversions begin after a hardw...

Page 1041: ...ter is actively controlling a conversion aborts the current conversion The SC1B SC1n registers are not used for software trigger operation and therefore writes to the SC1B SC1n registers do not initia...

Page 1042: ...10 bit Mode 24 ADC Cycles 12 bit Mode 28 ADC Cycles Single or First continuous time adder 5 ADC cycles 5 bus clock cycles 38 5 4 6 Hardware average function The hardware average function can be enabl...

Page 1043: ...r than OR equal to CV1 registers 0 1 Less than or equal Outside range not inclusive Compare true if the result is less than CV1 OR the result is greater than CV2 0 1 Greater than Inside range not incl...

Page 1044: ...sult in ADC conversion results with lower than specified accuracy In order to calibrate the ADC correctly the following has to be done On startup wait until the reference voltage VREFH has stabilized...

Page 1045: ...r than the maximum or less than the minimum result value it is forced to the appropriate limit for the current mode of operation The formatting of OFS is different from the data result register Rn to...

Page 1046: ...n the MCU enters Normal Stop mode it continues until completion Conversions can be initiated while the MCU is in Normal Stop mode by means of the hardware trigger or if continuous conversions are enab...

Page 1047: ...mary this allow the CMP to operate independently in STOP1 and VLPS mode whilst being triggered periodically to sample up to 8 inputs Only if an input changes state is a full wakeup generated In sectio...

Page 1048: ...nel 7 Input CMP0_RRT Round robin active signal Output CMP0_OUT Comparator output to PAD and TRGMUX Output 39 1 3 CMP external references The CMP could get external reference through the tightly integr...

Page 1049: ...the delay is 1 2 Prescaler output period In Time Counter mode with prescaler bypassed the delay is 1 2 Prescaler source clock period The delay between the first signal from LPTMR and the second signa...

Page 1050: ...cuting WFI 39 2 Introduction The comparator CMP module provides a circuit for comparing two analog input voltages The comparator circuit is designed to operate across the full range of the supply volt...

Page 1051: ...led Windowed which is ideal for certain PWM zero crossing detection applications Digitally filtered Filter can be bypassed Can be clocked via external SAMPLE signal or scaled bus clock External hyster...

Page 1052: ...ce source Power Down mode to conserve power when not in use Option to route the output to internal comparator input 39 3 3 ANMUX key features The ANMUX has the following features Two 8 to 1 channel MU...

Page 1053: ...Input 3 Reference Input 4 Reference Input 5 Reference Input 6 INP INN Reference Input 7 INPSEL 1 0 INNSEL 1 0 01 00 01 00 CHNx Round robin switch FXMXCH 2 0 1 0 From round robin switch 1 0 RRE RRE Fi...

Page 1054: ...hen C0 WE 0 If C0 WE 1 the comparator output is sampled on every bus clock when WINDOW 1 to generate COUTA Sampling does NOT occur when WINDOW 0 The Filter block is bypassed when not in use FILT_PER F...

Page 1055: ...y CMP_C1 INPSEL and CMP_C1 INNSEL The output of the second multiplex will finally go to the positive and negative ports of the comparator respectively Table 39 3 CMP signal descriptions Signal Descrip...

Page 1056: ...C0 WE When set the comparator output is sampled only when WINDOW 1 This feature can be used to ignore the comparator output during time periods in which the input voltages are not valid This is especi...

Page 1057: ...g bus clock edge when SAMPLE 1 to generate COUTA which is then resampled and filtered to generate COUT See the Windowed Filtered mode 7 All other combinations of C0 EN C0 WE C0 SE C0 FILTER_CNT and C0...

Page 1058: ...f sample window input The analog comparator block is powered and active CMPO may be optionally inverted but is not subject to external sampling or filtering Both window control and filter blocks are c...

Page 1059: ...ve The path from analog inputs to COUTA is combinational unclocked Windowing control is completely bypassed COUTA is sampled whenever a rising edge is detected on the filter block clock input The only...

Page 1060: ...wing figure illustrates comparator operation in this mode assuming the polarity select is set to non inverting state Sample Point CMPO COUT Figure 39 7 Sampled Non Filtered Mode Timing Diagram 39 7 4...

Page 1061: ...UTA 1 WE 0 SE 1 CGMUX COS 1 0 FILT_PER bus clock COS IER F CFR F WINDOW SAMPLE 1 0 EN PMODE HYSTCTR 1 0 divided bus clock CMPO 0x01 Internal bus Polarity select Window control Filter block Interrupt c...

Page 1062: ...that now C0 FILTER_CNT 1 which activates filter operation 39 7 5 Windowed mode s 5A 5B The following figure illustrates comparator operation in the Windowed mode ignoring latency of the analog compar...

Page 1063: ...Window control Filter block Interrupt control divided bus clock Clock prescaler CMPO Internal bus To other SOC functions Figure 39 11 Windowed mode For control configurations which result in disablin...

Page 1064: ...ding upon the sampling rate and window placement COUT may not see zero crossing events detected by the analog comparator Sampling period and or window placement must be carefully considered for a give...

Page 1065: ...is clocked by the bus clock whenever WINDOW 1 The last latched value is held when WINDOW 0 IRQ EN PMODE HYSCTR 1 0 INP INM FILTER_CNT INV COUT COUT OPE SE CMPO to PAD COUTA 0 1 WE 1 0 SE 0 CGMUX COS 0...

Page 1066: ...its Access Reset value Section page 4007_3000 CMP Control Register 0 CMP0_C0 32 R W 0000_0000h 39 8 1 1066 4007_3004 CMP Control Register 1 CMP0_C1 32 R W 0000_0000h 39 8 2 1070 4007_3008 CMP Control...

Page 1067: ...value 0 30 DMAEN DMA Enable Enables the DMA transfer triggered from the CMP module When this field is set a DMA request is asserted when CFR or CFF is set 0 DMA is disabled 1 DMA is enabled 29 Reserv...

Page 1068: ...comparator output filter when C0 SE 0 Setting FPR to 0x0 disables the filter Filter programming and latency details are provided in the CMP functional description This field has no effect when C0 SE...

Page 1069: ...mes no power 0 Analog Comparator is disabled 1 Analog Comparator is enabled 7 Reserved This field is reserved This read only field is reserved and always has the value 0 6 4 FILTER_CNT Filter Sample C...

Page 1070: ...el 1 hysteresis internally 10 The hard block output has level 2 hysteresis internally 11 The hard block output has level 3 hysteresis internally 39 8 2 CMP Control Register 1 CMPx_C1 Access Supervisor...

Page 1071: ...robin mode If the same channel is selected as the reference voltage this bit has no effect 22 CHN6 Channel 6 input enable Channel 6 of the input enable for the round robin checker If CHN6 is set then...

Page 1072: ...rve power 0 DAC is disabled 1 DAC is enabled 14 VRSEL Supply Voltage Reference Source Select 0 Vin1 is selected as resistor ladder network supply reference Vin 1 Vin2 is selected as resistor ladder ne...

Page 1073: ...l Register 2 CMPx_C2 Access Supervisor read write User read write Address 4007_3000h base 8h offset 4007_3008h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R RRE RRIE FXMP 0 FXMXCH 0 CH7F CH6F...

Page 1074: ...elected as the fixed reference input for the fixed mux port 101 Channel 5 is selected as the fixed reference input for the fixed mux port 110 Channel 6 is selected as the fixed reference input for the...

Page 1075: ...s 100kHz then INITMOD should be set to 80us 10us 8 000000 The modulus is set to 64 same with 111111 other values Initialization delay is set to INITMOD round robin clock period ACOn The result of the...

Page 1076: ...enerates the filtered and synchronized output COUT Both COUTA and COUT can be configured as module outputs and are used for different purposes within the system Synchronization and edge detection are...

Page 1077: ...rupt only one sample The value of C0 FILTER_CNT must be chosen to reduce the probability of noisy samples causing an incorrect transition to be recognized The probability of an incorrect transition is...

Page 1078: ...the rising or falling edge of the comparator output or both Assuming the CMP DMA enable bit is not set the following table gives the conditions in which the interrupt request is asserted and deasserte...

Page 1079: ...to 1 multiplexer which selects an output voltage from one of 256 distinct levels that outputs from DACO It is controlled through the Control register 1 CMP_C1 Its supply reference source can be select...

Page 1080: ...put in a round robin manner In order to meet the comparator stabilization time after the configurable number of operation clocks defined by C2 NSAM the comparison result is sampled for the selected ch...

Page 1081: ...d to not select the internal reserved channels for round robin by INPSEL and INNSEL NOTE In round robin mode it is suggested to always configure the DAC output as the fixed port reference NOTE In roun...

Page 1082: ...el decoded from PSEL 2 0 Channel decoded from MSEL 2 0 Channel 0 7 can be compared with channel 0 72 Trigger Mode 1 x x 0 1 0 x 0 7 DAC Channel sweep CHNx Channel 0 7 can be swept with DAC x x 1 0 1 x...

Page 1083: ...S 4 1 1 8 PDB has slots also referred as PDB channels for connectivity with chip Each slot consists of pulse out triggers and pre triggers as mentioned in above table See Figure 40 6 and Figure 37 2 4...

Page 1084: ...igger connects to ADC Pulse out Pulse out connects to TRGMUX 40 1 3 Back to back acknowledgement connections Back to back operation enables the ADC conversions complete to trigger the next PDB channel...

Page 1085: ...ger 1 PDB1 CH 0 pre trigger 2 PDB1 CH 0 pre trigger 7 PDB1 CH 0 pre trigger 6 PDB1 CH 0 pre trigger 4 PDB1 CH 0 pre trigger 5 PDB1 CH 0 pre trigger 3 Figure 40 2 Example PDB1 CH0 back to back chain Wh...

Page 1086: ...gger 1 PDB1 CH 0 pre trigger 2 PDB1 CH 0 pre trigger 7 PDB1 CH 0 pre trigger 6 PDB1 CH 0 pre trigger 4 PDB1 CH 0 pre trigger 5 PDB1 CH 0 pre trigger 3 Figure 40 3 PDB back to back chain forming PDB0 P...

Page 1087: ...ADC0 SC1D_COCO 5 ADC0 SC1E_COCO ADC0 SC1E_COCO 6 ADC0 SC1F_COCO ADC0 SC1F_COCO 7 ADC0 SC1G_COCO ADC0 SC1G_COCO PDB0 CH1 0 ADC0 SC1P_COCO 1 1 ADC0 SC1I_COCO 2 ADC0 SC1J_COCO 3 ADC0 SC1K_COCO 4 ADC0 SC...

Page 1088: ...C1F_COCO 7 ADC1 SC1G_COCO ADC1 SC1G_COCO PDB1 CH1 0 ADC1 SC1P_COCO 1 1 ADC1 SC1I_COCO 2 ADC1 SC1J_COCO 3 ADC1 SC1K_COCO 4 ADC1 SC1L_COCO 5 ADC1 SC1M_COCO 6 ADC1 SC1N_COCO 7 ADC1 SC1O_COCO PDB1 CH2 0 A...

Page 1089: ...k Pre trigger ADC1 SC1H ADHWTS7 COCO PDB0 CH1 Pre trigger 0 Ack Pre trigger ADC0 SC1I ADHWTS8 COCO PDB1 CH1 Pre trigger 0 Ack Pre trigger ADC1 SC1I ADHWTS8 COCO PDB0 CH1 Pre trigger 1 Ack Pre trigger...

Page 1090: ...ADHWTS15 COCO PDB0 CH3 Pre trigger 0 Ack Pre trigger ADC0 SC1Y ADHWTS8 COCO PDB1 CH3 Pre trigger 0 Ack Pre trigger ADC1 SC1Y ADHWTS8 COCO PDB0 CH3 Pre trigger 1 Ack Pre trigger ADC0 SC1Z ADHWTS9 COCO...

Page 1091: ...ts of ADCs The PDB can optionally provide pulse outputs Pulse Out s that are used as the sample window in the CMP block 40 2 1 Features Up to 2 trigger input sources and one software trigger source Up...

Page 1092: ...N Total available number of PDB channels n PDB channel number valid from 0 to N 1 M Total available pre trigger per PDB channel m Pre trigger number valid from 0 to M 1 Y Total number of Pulse Out s y...

Page 1093: ...EN m MULT Ack m Pre trigger m Sequence Error Detection ERR M 1 0 PRESCALER PDBCNT PDBMOD CONT PDBIDLY PDB interrupt TOEx POyDLY2 POyDLY1 Pulse Generation Pulse Out y PDBPOEN y Pulse Out y Control log...

Page 1094: ...event Enabled Bypassed The pre trigger and trigger outputs assert immediately after a positive edge on the selected trigger input source or software trigger is selected and SC SWTRIG is written with...

Page 1095: ..._CH1DLY4 32 R W 0000_0000h 40 3 11 1107 4003_1054 Channel n Delay 5 register PDB1_CH1DLY5 32 R W 0000_0000h 40 3 12 1107 4003_1058 Channel n Delay 6 register PDB1_CH1DLY6 32 R W 0000_0000h 40 3 13 110...

Page 1096: ...T 32 R 0000_0000h 40 3 3 1101 4003_600C Interrupt Delay register PDB0_IDLY 32 R W 0000_FFFFh 40 3 4 1102 4003_6010 Channel n Control register 1 PDB0_CH0C1 32 R W 0000_0000h 40 3 5 1102 4003_6014 Chann...

Page 1097: ...0_CH2DLY4 32 R W 0000_0000h 40 3 11 1107 4003_607C Channel n Delay 5 register PDB0_CH2DLY5 32 R W 0000_0000h 40 3 12 1107 4003_6080 Channel n Delay 6 register PDB0_CH2DLY6 32 R W 0000_0000h 40 3 13 11...

Page 1098: ...0 0 0 0 0 0 0 0 0 0 0 0 PDBx_SC field descriptions Field Description 31 20 Reserved This field is reserved This read only field is reserved and always has the value 0 19 18 LDMOD Load Mode Select Sel...

Page 1099: ...ipheral clock MULT x PRESCALAR 000 Counting uses the peripheral clock divided by MULT the multiplication factor 001 Counting uses the peripheral clock divided by 2 x MULT the multiplication factor 010...

Page 1100: ...n factor is 20 11 Multiplication factor is 40 1 CONT Continuous Mode Enable Enables the PDB operation in Continuous mode 0 PDB operation in One Shot mode 1 PDB operation in Continuous mode 0 LDOK Load...

Page 1101: ...0 MOD PDB Modulus Specifies the period of the counter When the counter reaches this value it will be reset back to zero If the PDB is in Continuous mode the count begins anew Reading this field retur...

Page 1102: ...field is reserved This read only field is reserved and always has the value 0 IDLY PDB Interrupt Delay Specifies the delay value to schedule the PDB interrupt It can be used to schedule an independen...

Page 1103: ...er a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1 1 PDB channel s corresponding pre trigger asserts when the counter reaches th...

Page 1104: ...values written to the register are written to its internal buffer instead in other words the internal device bus does not write directly to this register The value in this register s internal buffer...

Page 1105: ...nel Delay These bits specify the delay value for the channel s corresponding pre trigger The pre trigger asserts when the counter is equal to DLY Reading these bits returns the value of internal regis...

Page 1106: ...r The value in this register s internal buffer is loaded into this register only after 1 is written to the SC LDOK bit Address Base address 24h offset 40d i where i 0d to 3d Bit 31 30 29 28 27 26 25 2...

Page 1107: ...nel Delay These bits specify the delay value for the channel s corresponding pre trigger The pre trigger asserts when the counter is equal to DLY Reading these bits returns the value of internal regis...

Page 1108: ...r The value in this register s internal buffer is loaded into this register only after 1 is written to the SC LDOK bit Address Base address 30h offset 40d i where i 0d to 3d Bit 31 30 29 28 27 26 25 2...

Page 1109: ...as the value 0 DLY PDB Channel Delay These bits specify the delay value for the channel s corresponding pre trigger The pre trigger asserts when the counter is equal to DLY Reading these bits returns...

Page 1110: ...rnal register that is effective for the current PDB cycle DLY2 PDB Pulse Out Delay 2 These bits specify the delay 2 value for the PDB Pulse Out Pulse Out goes low when the PDB counter is equal to the...

Page 1111: ...ms shown in the following diagram show the pre trigger and trigger outputs of PDB channel n The delays can be independently set using the channel delay registers CHnDLYm and the pre triggers can be en...

Page 1112: ...e error interrupt is generated A sequence error typically happens because the delay m is set too short and the pre trigger m asserts before the previously triggered ADC conversion finishes If the pre...

Page 1113: ...ulse outputs of configurable width When the PDB counter reaches the value set in POyDLY DLY1 then the Pulse Out goes high When the PDB counter reaches POyDLY DLY2 then it goes low POyDLY DLY2 can be s...

Page 1114: ...40 8 How Pulse Out is generated 40 4 4 Updating the delay registers The following registers control the timing of the PDB operation and in some of the applications they may need to become effective a...

Page 1115: ...trigger input event is detected after 1 is written to SC LDOK 11 Either the PDB counter reaches PDB_MOD MOD 1 value or a trigger input event is detected after 1 is written to SC LDOK After 1 is writt...

Page 1116: ...es the interrupts Table 40 8 PDB interrupt summary Interrupt Flags Enable bit PDB Interrupt SC PDBIF SC PDBIE 1 and SC DMAEN 0 PDB Sequence Error Interrupt CHnS ERRm SC PDBEIE 1 40 4 6 DMA If SC DMAEN...

Page 1117: ...lues of total peripheral clocks that can be detected are even values if prescaler is set to 4 then the only values of total peripheral clocks that can be decoded as detected are mod 4 and so forth If...

Page 1118: ...Application information MWCT101xS Series Reference Manual Rev 3 07 2019 1118 NXP Semiconductors...

Page 1119: ...coder Hall sensor support Dithering WCT1014 S FTM0 8 4 Yes No No No FTM1 8 4 No Yes Yes No FTM2 8 4 No Yes Yes No FTM3 8 4 Yes No No No WCT1015 S FTM0 8 4 Yes No No No FTM1 8 4 No Yes Yes Yes FTM2 8 4...

Page 1120: ...ources of interrupt Refer to the MWCT101xS_DMA_Interrupt_mapping xlsm attached with this Reference Manual When an FTM interrupt occurs read the FTM status registers FMS SC and STATUS to determine the...

Page 1121: ...FLT0 pin FTM7 FAULT1 FTM7_FLT1 pin FTMx_FLT0 Trigger source_0 TRGMUX Trigger source_1 Trigger source_n FTMx FTMx_FLT1 FTMx_FLT2 FTMx_FLT3 FTMxFLT0SEL FTMxFLT1SEL FTMxFLT2SEL FAULT0 FAULT1 FAULT2 FAULT...

Page 1122: ...3SYNCBIT FTM3 hardware trigger 2 FTM3_FLT0 pin FTM4 FTM4 hardware trigger 0 TRGMUX trigger output FTM4 hardware trigger 1 SIM_FTMOPT1 FTM4SYNCBIT FTM4 hardware trigger 2 FTM4_FLT0 pin FTM5 FTM5 hardwa...

Page 1123: ...ext_trig FTM2 init_trig hw_trig ext_trig FTM3 ADC0 ADC1 init_trig hw_trig ext_trig FTM4 init_trig hw_trig ext_trig FTM5 init_trig hw_trig ext_trig FTM6 init_trig hw_trig ext_trig FTM7 init_trig hw_tr...

Page 1124: ...to an input capture pin can then be analyzed and both speed and position can be deduced To simplify the calculations required by the CPU on each hall sensor s input if all 3 inputs are exclusively OR...

Page 1125: ...trolled by SIM_FTMOPT1 FTM3CHySEL on each of its 8 channels with modulation possible via FTM2_CH1 See SIM chapter for further information When FTM1_CH1 is used to modulate an FTM0 channel then the use...

Page 1126: ...2 FTM3 gtb_in gtb_in gtb_in gtb_in gtb_in gtb_in gtb_in gtb_in SIM_MISCTRL0 14 SIM_MISCTRL0 14 0 1 0 1 gtb_out gtb_out gtb_out gtb_out FTM4 FTM5 FTM6 FTM7 gtb_out gtb_out gtb_out gtb_out Figure 41 5 F...

Page 1127: ...ock connects FTM clock to a chip level input pin therefore allowing to synchronize the FTM counter with an off chip clock source Prescaler divide by 1 2 4 8 16 32 64 or 128 16 bit counter It can be a...

Page 1128: ...the fault condition is detected The generation of an interrupt when a register reload point occurs Synchronized loading of write buffered FTM registers Half cycle and Full cycle register reload capac...

Page 1129: ...41 2 3 Block Diagram The FTM uses one input output I O pin per channel CHn FTM channel n where n is the channel number 0 7 NOTE The number of channels supported can vary for each instance of the FTM...

Page 1130: ...adtime insertion output mask fault control and polarity control output modes logic input capture mode prescaler 1 2 4 8 16 32 64 or 128 DECAPEN MCOMBINE0 COMBINE0 CPWMS MS0B MS0A ELS0B ELS0A MS1B MS1A...

Page 1131: ...at each FAULTj input may affect all channels selectively since FAULTM 1 0 and FAULTEN control bits are defined for each pair of channels Because there are several FAULTj inputs maximum of 4 for the FT...

Page 1132: ...se address 4003_8000h FTM1 base address 4003_9000h FTM2 base address 4003_A000h FTM3 base address 4002_6000h FTM4 base address 4006_E000h FTM5 base address 4006_F000h FTM6 base address 4007_0000h FTM7...

Page 1133: ...0000_0000h 68h Deadtime Configuration DEADTIME 32 RW 0000_0000h 6Ch FTM External Trigger EXTTRIG 32 RW 0000_0000h 70h Channels Polarity POL 32 RW 0000_0000h 74h Fault Mode Status FMS 32 RW 0000_0000h...

Page 1134: ...trols relate to all channels within this module 41 4 3 2 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 FLTP S PWMEN7 PWMEN6 PWMEN5 PWMEN4 PWMEN3 PWMEN2 PWMEN1 PWMEN0 W Reset 0 0 0...

Page 1135: ...other FTM overflow occurs between the read and write operations the write operation has no effect therefore TOF remains set indicating an overflow has occurred In this case a TOF interrupt request is...

Page 1136: ...y clock 11b External clock 2 0 PS Prescale Factor Selection Selects one of 8 division factors for the clock source selected by CLKS The new prescaler factor affects the clock source on the next FTM in...

Page 1137: ...ontains the modulo value for the FTM counter After the FTM counter reaches the modulo value the overflow flag TOF becomes set at the next clock cycle and the next value of FTM counter depends on the s...

Page 1138: ...10 9 8 7 6 5 4 3 2 1 0 R MOD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 4 3 4 4 Fields Field Function 31 16 Reserved 15 0 MOD MOD Modulo Value 41 4 3 5 Channel n Status And Control C0SC C7SC 41 4 3 5...

Page 1139: ...and not the channel n input value this signal is the input signal used by the dual edge mode 0b The channel n input is zero 1b The channel n input is one 8 TRIGMODE Trigger mode control This bit cont...

Page 1140: ...l n Edge or Level Select Used on the selection of the channel n mode See Channel Modes This field is write protected It can be written only when MODE WPDIS 1 2 ELSA Channel n Edge or Level Select Used...

Page 1141: ...a write to CnSC register resets manually this write coherency mechanism 41 4 3 6 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14...

Page 1142: ...ehavior before the first write to select the FTM clock write the new value to the CNTIN register and then initialize the FTM counter by writing any value to the CNT register 41 4 3 7 3 Diagram Bits 31...

Page 1143: ...g a 0 to the CHF bit Writing a 1 to CHF has no effect If another event occurs between the read and write operations the write operation has no effect therefore CHF remains set indicating an event has...

Page 1144: ...control mode and interrupt Capture Test mode PWM synchronization Write protection Channel output initialization These controls relate to all channels within this module 41 4 3 9 3 Diagram Bits 31 30...

Page 1145: ...ynchronization when SYNCMODE is 0 0b No restrictions Software and hardware triggers can be used by MOD CnV OUTMASK and FTM counter synchronization 1b Software trigger can only be used by MOD and CnV s...

Page 1146: ...oftware triggers but not both at the same time otherwise unpredictable behavior is likely to happen The selection of the loading point CNTMAX and CNTMIN bits is intended to provide the update of MOD C...

Page 1147: ...is enabled 5 TRIG1 PWM Synchronization Hardware Trigger 1 Enables hardware trigger 1 to the PWM synchronization Hardware trigger 1 happens when a rising edge is detected at the trigger 1 input signal...

Page 1148: ...enabled 0 CNTMIN Minimum Loading Point Enable Selects the minimum loading point to PWM synchronization Synchronization Points If CNTMIN is 1 the selected loading point is when the FTM counter reaches...

Page 1149: ...or BLDC control where the PWM signal is presented to an electric motor at specific times to provide electronic commutation Any write to the OUTMASK register stores the value in its write buffer The re...

Page 1150: ...figuration bits for each pair of channels 41 4 3 13 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R MCOMBINE3 FAULTEN3 SYNCEN3 DTEN3 DECAP3 DECAPEN3 COMP3 COMBINE3 MCOMBINE2 FAULTEN2...

Page 1151: ...uration of the dual edge capture bits This field applies only when DECAPEN 1 DECAP bit is cleared automatically by hardware if dual edge capture one shot mode is selected and when the capture of chann...

Page 1152: ...l edge capture one shot mode is selected and when the capture of channel n 1 event is made 0b The dual edge captures are inactive 1b The dual edge captures are active 18 DECAPEN2 Dual Edge Capture Mod...

Page 1153: ...bles the Dual Edge Capture mode in the channels n and n 1 See Channel Modes This field is write protected It can be written only when MODE WPDIS 1 9 COMP1 Complement Of Channel n For n 2 In Complement...

Page 1154: ...The dual edge captures are active 2 DECAPEN0 Dual Edge Capture Mode Enable For n 0 Enables the Dual Edge Capture mode in the channels n and n 1 See Channel Modes This field is write protected It can b...

Page 1155: ...EX DTVAL Deadtime insert value DTPS DTVALEX DTVAL This field is write protected It can be written only when MODE WPDIS 1 NOTE If full compatibility is needed with previous software versions write 0 to...

Page 1156: ...0 9 8 7 6 5 4 3 2 1 0 R 0 CH7TRIG CH6TRIG TRIGF INITTRIGEN CH1TRIG CH0TRIG CH5TRIG CH4TRIG CH3TRIG CH2TRIG W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 4 3 15 4 Fields Field Function 31 10 Reserved 9...

Page 1157: ...4 CH0TRIG Channel 0 External Trigger Enable Enables the generation of the external trigger when FTM counter C0V 0b The generation of this external trigger is disabled 1b The generation of this externa...

Page 1158: ...1 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 POL7 POL6 POL5 POL4 POL3 POL2 POL1 POL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 4 3 16 4...

Page 1159: ...LTF WPEN FAULTIN 0 FAULTF3 FAULTF2 FAULTF1 FAULTF0 W 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 4 3 17 4 Fields Field Function 31 8 Reserved 7 FAULTF Fault Detection Flag Represents the logic...

Page 1160: ...en fault control is enabled the corresponding fault input is enabled and a fault condition is detected at the fault input Clear FAULTF3 by reading the FMS register while FAULTF3 is set and then writin...

Page 1161: ...n at the corresponding fault input Writing a 1 to FAULTF1 has no effect FAULTF1 bit is also cleared when FAULTF bit is cleared If another fault condition is detected at the corresponding fault input b...

Page 1162: ...ssing valid signal 41 4 3 18 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CH3FVAL CH2FVAL CH1...

Page 1163: ...FLTCTRL 7Ch 41 4 3 19 2 Function This register contains the state of channels output when a fault event happens the enable for each fault input the filter enable for each fault input the filter value...

Page 1164: ...ult in a missing fault detection 7 FFLTR3EN Fault Input 3 Filter Enable Enables the filter for the fault input This field is write protected It can be written only when MODE WPDIS 1 NOTE This field is...

Page 1165: ...protected It can be written only when MODE WPDIS 1 0b Fault input filter is disabled 1b Fault input filter is enabled 3 FAULT3EN Fault Input 3 Enable Enables the fault input This field is write protec...

Page 1166: ...s the fault input This field is write protected It can be written only when MODE WPDIS 1 0b Fault input is disabled 1b Fault input is enabled 0 FAULT0EN Fault Input 0 Enable Enables the fault input Th...

Page 1167: ..._ QDCT RL FTM7_ QDCT RL 41 4 3 20 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PHAFLTREN PH...

Page 1168: ...Field supported in Field not supported in FTM1_QDCTRL FTM2_QDCTRL FTM4_QDCTRL 0b Phase B input filter is disabled 1b Phase B input filter is enabled 5 PHAPOL Phase A Input Polarity Selects the polarit...

Page 1169: ...register to its minimum value CNTIN register 0 QUADEN Quadrature Decoder Mode Enable Enables the Quadrature Decoder mode In this mode the phase A and B input signals control the FTM counter direction...

Page 1170: ...time base signal generation to other FTMs 0b A global time base signal generation is disabled 1b A global time base signal generation is enabled 9 GTBEEN Global Time Base Enable Configures the FTM to...

Page 1171: ...ram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 FLT3POL FLT2POL FLT1POL FLT0POL W Reset 0 0 0 0 0 0...

Page 1172: ...M3_FLTPOL FTM4_FLTPOL FTM5_FLTPOL FTM6_FLTPOL FTM7_FLTPOL 0b The fault input polarity is active high A 1 at the fault input indicates a fault 1b The fault input polarity is active low A 0 at the fault...

Page 1173: ...0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SWSOC SWINVC SWOM SWWRBU F SWRSTCNT SYNCMODE 0 SWOC INVC 0 CNTINC 0 HWTRIGMODE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 4 3 23 4 Fields Field Funct...

Page 1174: ...ftware trigger 0b The software trigger does not activate the OUTMASK register synchronization 1b The software trigger activates the OUTMASK register synchronization 9 SWWRBUF MOD HCR CNTIN and CV regi...

Page 1175: ...channel n output Each INVmEN bit enables the inverting operation for the corresponding pair channels m This register has a write buffer The INVmEN bit is updated by the INVCTRL register synchronizati...

Page 1176: ...M Software Output Control SWOCTRL 41 4 3 25 1 Offset Register Offset SWOCTRL 94h 41 4 3 25 2 Function This register enables software control of channel n output and defines the value forced to the cha...

Page 1177: ...Output Control Enable 0b The channel output is not affected by software output control 1b The channel output is affected by software output control 41 4 3 26 FTM PWM Load PWMLOAD 41 4 3 26 1 Offset Re...

Page 1178: ...l load mechanism implemented by GLDOK If GLEN bit is set then an external event on the FTM global load input sets the LDOK bit The clear of the LDOK bit is done by CPU writes 0 to the bit 0b Global Lo...

Page 1179: ...ed if FTM_PWMLOAD HCSEL is enabled Writing to the HCR register latches the value into a buffer The HCR register is updated with the value of its write buffer according to Registers updated from write...

Page 1180: ...0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 DTPS DTVAL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 4 3 28 4 Fields Field Function 31 20 Reserved 19 16 DTVALEX Extended Deadtime Value This field i...

Page 1181: ...ime Value Selects the deadtime value This field is write protected It can be written only when MODE WPDIS 1 41 4 3 29 Pair 1 Deadtime Configuration PAIR1DEADTIME 41 4 3 29 1 Offset Register Offset PAI...

Page 1182: ...FTM input clock This prescaled clock is used by the deadtime counter This field is write protected It can be written only when MODE WPDIS 1 0xb Divide the FTM input clock by 1 10b Divide the FTM input...

Page 1183: ...nsert value DTPS DTVALEX DTVAL This field is write protected It can be written only when MODE WPDIS 1 15 8 Reserved 7 6 DTPS Deadtime Prescaler Value Selects the division factor of the FTM input clock...

Page 1184: ...ines the 4 most significant bits of the deadtime value The maximum deadtime value is extended to 1023 using the concatenation DTVALEX DTVAL Deadtime insert value DTPS DTVALEX DTVAL This field is write...

Page 1185: ...ction This register contains the integer and fractional modulo value for the FTM counter NOTE Each module instance supports a different number of registers Register supported Register not supported FT...

Page 1186: ...r Value See the field MOD of the register MOD 15 11 FRACMOD Modulo Fractional Value The modulo fractional value is used in the PWM period dithering This value is added to an internal accumulator at th...

Page 1187: ...value of the channel n match NOTE Each module instance supports a different number of registers Register supported Register not supported FTM0_C 0V_ MIRR OR C7V_ MIRR OR FTM1_C 0V_ MIRR OR C7V_ MIRR...

Page 1188: ...28 27 26 25 24 23 22 21 20 19 18 17 16 R VAL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R FRACVAL 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 4 3 33 4 Fields F...

Page 1189: ...d The CLKS 1 0 bits may be read or written at any time Disabling the FTM counter by writing 0 0 to the CLKS 1 0 bits does not affect the FTM counter value or other registers The fixed frequency clock...

Page 1190: ...r clock is the selected clock divided by the prescaler The FTM counter has these modes of operation Up counting Up down counting Quadrature Decoder Mode 41 5 3 1 Up counting Up counting is selected wh...

Page 1191: ...k counter event counter event counter event Figure 41 8 Example of FTM up and signed counting Table 41 3 FTM counting based on CNTIN value When Then CNTIN 0x0000 The FTM counting is equivalent to TPM...

Page 1192: ...and MOD registers meet this requirement Any values of CNTIN and MOD that do not satisfy this criteria can result in unpredictable behavior MOD CNTIN is a redundant condition In this case the FTM count...

Page 1193: ...OD defines the final value of the count The value of CNTIN is loaded into the FTM counter and the counter increments until the value of MOD is reached at which point the counter is decremented until i...

Page 1194: ...r if CnV 0 or if CnV 15 1 In this case 0 CPWM is generated The figure below shows the possible counter events when in up down counting mode See Counter events for more details FTM counter 0 0 1 1 1 1...

Page 1195: ...TOF bit MOD 0x0000 counter event Figure 41 13 Example when the FTM counter is free running The FTM counter is also a free running counter when FTMEN 1 QUADEN 0 CPWMS 0 CNTIN 0x0000 and MOD 0xFFFF 41 5...

Page 1196: ...elect which point will be used to generate the counter event Figure at Up down counting shows the possible counter events FTM counter is reseted see Counter reset or a value different from zero is wri...

Page 1197: ...lses set Output on match 1 XX 10 Center Aligned PWM High true pulses clear Output on match up X1 Low true pulses set Output on match up 1 0 XX 10 Combine PWM High true pulses set on channel n match an...

Page 1198: ...1 1 Enabled Rising and falling edges 41 5 5 Input Capture Mode The Input Capture mode is selected when DECAPEN 0 MCOMBINE 0 COMBINE 0 CPWMS 0 MSB MSA 0 0 and ELSB ELSA 0 0 When a selected edge occurs...

Page 1199: ...channel n Figure 41 14 Diagram for Input Capture Mode when FLTPS 3 0 0 channel n input synchronizer 1 is filter enabled D CLK D CLK FTM input clock filter 0 Note The filter is only available for the...

Page 1200: ...The maximum frequency for the channel input to be detected correctly is FTM filter clock divided by 4 which is required to meet Nyquist criteria for signal sampling When there is a state change in the...

Page 1201: ...nnel input filter is enabled CHnFVAL 3 0 0 FLTPS 3 0 0 4 4 CHnFVAL 3 0 rising edges of FTM input clock FLTPS 3 0 0 4 rising edges of FTM input clock plus 1 4 CHnFVAL 3 0 rising edges of FTM filter clo...

Page 1202: ...0 41 5 5 2 FTM Counter Reset in Input Capture Mode If the channel n is in input capture mode and CnSC ICRST 1 then when the selected input capture event occurs in the channel n input signal the curre...

Page 1203: ...also reset 41 5 6 Output Compare mode The Output Compare mode is selected when DECAPEN 0 MCOMBINE 0 COMBINE 0 CPWMS 0 and MSB MSA 0 1 In Output Compare mode the FTM can generate timed pulses with prog...

Page 1204: ...ompare mode when the match clears the channel output channel n output CHF bit TOF bit CNT MOD 0x0005 CnV 0x0003 counter overflow channel n match counter overflow channel n match counter overflow 0 1 2...

Page 1205: ...el n match pulse width Figure 41 24 EPWM period and pulse width with ELSB ELSA 1 0 If ELSB ELSA 0 0 when the counter reaches the value in the CnV register the CHF bit is set and the channel n interrup...

Page 1206: ...le EPWM signal and CHF bit is not set even when there is the channel n match If CnV MOD then the channel n output is a 100 duty cycle EPWM signal and CHF bit is not set Therefore MOD must be less than...

Page 1207: ...her channel modes are not compatible with the up down counter CPWMS 1 Therefore all FTM channels must be used in CPWM mode when CPWMS 1 pulse width counter overflow FTM counter MOD period 2 x CnV CNTI...

Page 1208: ...008 CnV 0x0005 Figure 41 29 CPWM signal with ELSB ELSA X 1 If CnV 0x0000 or CnV is a negative value that is CnV 15 1 then the channel n output is a 0 duty cycle CPWM signal and CHF bit is not set even...

Page 1209: ...high at the channel n match FTM counter C n V See the following figure If channel n ELSB ELSA X 1 then the channel n output is forced high at the beginning of the period FTM counter CNTIN and at the...

Page 1210: ...utput with ELSB ELSA 1 0 channel n output with ELSB ELSA X 1 MOD C n 1 V C n V CNTIN Figure 41 32 Channel n output if CNTIN C n V MOD and C n 1 V MOD FTM counter C n 1 V channel n output with ELSB ELS...

Page 1211: ...C n V is Almost Equal to CNTIN and C n 1 V MOD FTM counter not fully 100 duty cycle channel n output with ELSB ELSA 1 0 channel n output with ELSB ELSA X 1 not fully 0 duty cycle MOD C n V CNTIN C n 1...

Page 1212: ...C n V and C n 1 V are not between CNTIN and MOD FTM counter 0 duty cycle channel n output with ELSB ELSA 1 0 channel n output with ELSB ELSA X 1 100 duty cycle MOD CNTIN C n 1 V C n V Figure 41 37 Ch...

Page 1213: ...LSB ELSA X 1 100 duty cycle 0 duty cycle MOD C n 1 V C n V Figure 41 39 Channel n output if C n V C n 1 V MOD channel n match is ignored FTM counter channel n output with ELSB ELSA 1 0 channel n outpu...

Page 1214: ...Figure 41 41 Channel n output if C n V CNTIN and CNTIN C n 1 V MOD C n 1 V channel n output with ELSB ELSA X 1 FTM counter CNTIN channel n output with ELSB ELSA 1 0 C n V MOD Figure 41 42 Channel n ou...

Page 1215: ...ure 41 43 Channel n output if C n V MOD and CNTIN C n 1 V MOD C n V CNTIN channel n output with ELSB ELSA X 1 channel n output with ELSB ELSA 1 0 FTM counter C n 1 V MOD Figure 41 44 Channel n output...

Page 1216: ...LSB ELSA X 1 0 duty cycle MOD C n V CNTIN C n 1 V Figure 41 46 Channel n output if C n V CNTIN and C n 1 V MOD 41 5 9 1 Asymmetrical PWM In Combine mode and Modified Combine PWM Mode the PWM first edg...

Page 1217: ...PWM Duty Cycle Condition 0 duty cycle For CNTIN C n V and C n 1 V MOD C n V C n 1 V duty cyle between 0 and 100 For CNTIN C n V and C n 1 V MOD if C n V C n 1 V then the duty cycle is C n 1 V C n V i...

Page 1218: ...d CNTIN MOD this situation happens when C n V C n 1 V FTM counter C n V match C n V is fixed channel n output with ELSB ELSA 1 0 C n 1 V is updated with its write buffer C n 1 V match 0 duty cycle Fig...

Page 1219: ...N CNTIN register update MOD MOD and HCR registers update C n V and C n 1 V CnV register update In the Modified Combine Mode if FTMEN 1 CLKS 1 0 0 0 and there was a write to the register C n 1 V then t...

Page 1220: ...COMP 0 channels n and n 1 are on Combine Mode or Modified Combine PWM Mode The channel n 1 output is independent from channel n output when QUADEN 0 DECAPEN 0 COMP 0 channel n is on Output Compare Mo...

Page 1221: ...er is written independent of FTMEN bit FTMEN 0 or CNTINC 0 At the next FTM input clock after CNTIN was written FTMEN 1 SYNCMODE 1 and CNTINC 1 By the CNTIN register synchronization CNTINC 1 and LDOK 1...

Page 1222: ...register is updated on the next FTM counter change end of the prescaler counting after CnV register was written If the selected mode is EPWM then CnV register is updated after CnV register was writte...

Page 1223: ...n with hardware trigger is initiated when a rising edge is detected at the enabled hardware trigger inputs If HWTRIGMODE 0 then the TRIGn bit is cleared when 0 is written to it or when the trigger n e...

Page 1224: ...cording to PWMSYNC and REINIT bits In this case if PWMSYNC 1 or PWMSYNC 0 and REINIT 0 then SWSYNC bit is cleared at the next selected loading point after that the software trigger event occurred see...

Page 1225: ...ter changes from MOD to MOD 1 FTM counter changes from CNTIN to CNTIN 1 synchronization points if CNTMIN 1 synchronization points if CNTMAX 1 up down counting mode FTM counter changes from MOD to CNTI...

Page 1226: ...ardware trigger SWWRBUF bit HWWRBUF bit SWSYNC bit SWRSTCNT bit wait the next selected loading point update MOD with its buffer value clear SWSYNC bit clear SWSYNC bit update MOD with its buffer value...

Page 1227: ...onization with SYNCMODE 0 PWMSYNC 0 REINIT 0 and software trigger was used selected loading point MOD register is updated write 1 to TRIG0 bit TRIG0 bit trigger 0 event FTM input clock Figure 41 57 MO...

Page 1228: ...ODE 0 PWMSYNC 0 REINIT 1 and a hardware trigger was used If SYNCMODE 0 and PWMSYNC 1 then this synchronization is made on the next selected loading point after the software trigger event takes place T...

Page 1229: ...ation mechanism is the same as the MOD register synchronization However it is expected that the C n V and C n 1 V registers be synchronized only by the enhanced PWM synchronization SYNCMODE 1 41 5 13...

Page 1230: ...dware trigger n TRIGn bit HWOM bit SWOM bit SWSYNC bit rising edge of FTM input clock update OUTMASK with its buffer value hardware trigger OUTMASK is updated by software trigger OUTMASK is updated by...

Page 1231: ...ware trigger event FTM input clock Figure 41 62 OUTMASK synchronization with SYNCMODE 0 SYNCHOM 1 PWMSYNC 0 and software trigger was used write 1 to TRIG0 bit TRIG0 bit trigger 0 event OUTMASK registe...

Page 1232: ...The INVCTRL register synchronization updates the INVCTRL register with its buffer value The INVCTRL register can be updated at each rising edge of FTM input clock INVC 0 or by the enhanced PWM synchro...

Page 1233: ...bit rising edge of FTM input clock update INVCTRL with its buffer value update INVCTRL with its buffer value HWINVC bit TRIGn bit wait hardware trigger n update INVCTRL with its buffer value HWTRIGMOD...

Page 1234: ...ger SWOCTRL is updated by hardware trigger enhanced PWM synchronization update SWOCTRL register by PWM synchronization update SWOCTRL register at each rising edge of FTM input clock yes 0 1 0 0 no 1 S...

Page 1235: ...l output from transitioning to 1 If no deadtime insertion is selected then the channel n 1 transitions to logical value 1 immediately after the synchronization event occurs synchronization event chann...

Page 1236: ...t hardware trigger TRIGn bit 0 0 0 0 0 1 Figure 41 68 FTM counter synchronization flowchart In the case of legacy PWM synchronization the FTM counter synchronization depends on REINIT and PWMSYNC bits...

Page 1237: ...FTM counter synchronization with SYNCMODE 0 HWTRIGMODE 0 REINIT 1 PWMSYNC 0 and a hardware trigger was used If SYNCMODE 0 REINIT 1 and PWMSYNC 1 then this synchronization is made on the next enabled...

Page 1238: ...is selected the channel n output behavior is changed to force high at the beginning of the PWM period force low at the channel n match and force high at the channel n 1 match See the following figure...

Page 1239: ...ter synchronization INV m bit channel n output after the inverting channel n 1 output after the inverting INV m bit selects the inverting to the pair channels n and n 1 channel n output before the inv...

Page 1240: ...annel n ELSB ELSA X 1 CH n OCV 1 and CH n 1 OCV 0 SWOCTRL register synchronization SWOCTRL register synchronization write to SWOCTRL register write to SWOCTRL register Figure 41 74 Example of software...

Page 1241: ...The clock for the DEADTIME delay is the FTM input clock divided by DTPS bits and the DTVALEX 3 0 DTVAL 5 0 bits define the deadtime modulo that is the number of the deadtime prescaler clocks The dead...

Page 1242: ...match channel n output before deadtime insertion channel n 1 output before deadtime insertion channel n output after deadtime insertion channel n 1 output after deadtime insertion channel n match Fig...

Page 1243: ...r 2 DTVALEX 3 0 DTPS 1 0 and DTVAL 5 0 0 1 Does the pair 3 have separated deadtime value register PAIR3DEADTIME pair 3 DTVALEX 3 0 DTPS 1 0 and DTVAL 5 0 Figure 41 77 Separated Deadtime by Pair of Cha...

Page 1244: ...ue Although in most cases the deadtime delay is not comparable to channels n and n 1 duty cycle the following figures show examples where the deadtime delay is comparable to the duty cycle FTM counter...

Page 1245: ...t mask The output mask can be used to force channels output to their inactive state through software For example to control a BLDC motor Any write to the OUTMASK register updates its write buffer The...

Page 1246: ...utput Mask Input Output Mask Result 0 inactive state inactive state active state active state 1 inactive state inactive state active state 41 5 18 Fault Control The fault control is enabled if FAULTM...

Page 1247: ...Fault Control when FLTPS 3 0 0 When there is a state change in the fault input n the counter is reset and starts counting up As long as the new state is stable on the fault input n the counter continu...

Page 1248: ...are enabled and the selected edge at the fault input n is detected then a fault condition has occurred and the FAULTFn bit is set The FAULTF bit is the logic OR of FAULTFn 3 0 bits See the following f...

Page 1249: ...ing of new PWM cycles FAULTF bit FAULTF bit is cleared The channel n output is after the fault control with automatic fault clearing and POLn 0 NOTE Figure 41 84 Fault control with automatic fault cle...

Page 1250: ...j input polarity is high so the logical one at the fault input j indicates a fault If FLTjPOL 1 the fault j input polarity is low so the logical zero at the fault input j indicates a fault 41 5 19 Pol...

Page 1251: ...1 1 is forced to one is forced to one The following table shows the values that channels n and n 1 are forced by initialization when COMP 1 or DTEN 1 Table 41 17 Initialization behavior when COMP 1 or...

Page 1252: ...put channel n ELSA channel n MSA channel n MSB channel n 1 MSB channel n 1 MSA channel n 1 ELSB channel n 1 ELSA channel n CHOV channel n 1 CHOV Figure 41 86 Priority of the features used at the gener...

Page 1253: ...er cycle This feature is controlled by the bits INITTRIGEN and ITRIGR The INITTRIGEN bit enables the initialization trigger generation and the ITRIGR bit selects when the initialization trigger is gen...

Page 1254: ...x000F INITTRIGEN 0 ITRIGR 0 Figure 41 89 Example of the generation of the initialization trigger in the case 2 NOTE This behavior is not available in CPWM mode 3 When there is the FTM counter synchron...

Page 1255: ...in Input Capture mode ICRST 1 and the selected input capture event occurs in the channel n input FTM input clock FTM counter channel n input CHF bit C n V XX 0x27 selected channel n input event rising...

Page 1256: ...is updated with its next value according to its configuration Its next value depends on CNTIN MOD and the written value to FTM counter The next reads of CnV registers return the written value to the...

Page 1257: ...19 Clear CHF bit when DMA 1 CHIE How CHF Bit Can Be Cleared 0 CHF bit is cleared either when the channel DMA transfer is done or by reading CnSC while CHF is set and then writing a 0 to CHF bit 1 CHF...

Page 1258: ...ed If the selected edge by channel n bits is detected at channel n input then channel n CHF bit is set and the channel n interrupt is generated if channel n CHIE 1 If the selected edge by channel n 1...

Page 1259: ...Capture mode The Continuous Capture mode is selected when DECAPEN 1 and channel n MSA 1 In this capture mode the edges at the channel n input are captured continuously The channel n ELSB ELSA bits sel...

Page 1260: ...the Dual Edge Capture One Shot mode used to measure the positive polarity pulse width The DECAPEN bit selects the Dual Edge Capture mode so it remains set The DECAP bit is set to enable the measureme...

Page 1261: ...ture One Shot mode for positive polarity pulse width measurement The following figure shows an example of the Dual Edge Capture Continuous mode used to measure the positive polarity pulse width The DE...

Page 1262: ...26 4 Period measurement If the channels n and n 1 are configured to capture consecutive edges of the same polarity then the period of the channel n input signal is measured If both channels n and n 1...

Page 1263: ...DECAPEN set DECAP clear channel n CHF and clear channel n 1 CHF are made by the user 4 9 11 12 13 14 6 15 16 17 18 19 20 21 22 23 24 25 26 27 28 17 20 15 20 23 C n V channel n 1 CHF bit channel n CHF...

Page 1264: ...bit clear channel n CHF 1 8 12 22 24 11 19 21 23 25 27 23 20 19 17 7 9 11 13 15 6 8 10 12 16 14 24 22 20 18 26 25 21 Figure 41 99 Dual Edge Capture Continuous mode to measure of the period between two...

Page 1265: ...counter value when the event 1 occurred and the read of C n 1 V returns the FTM counter value when the event 2 occurred read C n 1 V FTM counter channel n input after the filter channel input channel...

Page 1266: ...FTM counter 0 1 FTM input clock is filter enabled FTM input clock CLK D CLK D Q FTM filter clock filter 0 1 is filter enabled Q FTM filter clock Figure 41 102 Diagram for Quadrature Decoder when FLTPS...

Page 1267: ...M counter is updated when there is a rising edge at phase A input signal phase B counting direction phase A counting rate FTM counter increment decrement FTM counter MOD CNTIN 0x0000 Time 1 1 1 1 1 1...

Page 1268: ...at phase A signal and phase B signal is at logic one phase A phase B FTM counter increment decrement FTM counter MOD CNTIN 0x0000 Time 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1...

Page 1269: ...e FTM counter overflow occurred TOFDIR indicates the counting was down when the FTM counter overflow occurred phase A phase B FTM counter increment decrement FTM counter MOD CNTIN 0x0000 Time set TOF...

Page 1270: ...igure 41 108 Motor position jittering near maximum and minimum count value The first highlighted transition causes a jitter on the FTM counter value near the maximum count value MOD The second indicat...

Page 1271: ...Stopped is not set The channels outputs are frozen when the chip enters in Debug mode Writes to these registers bypass the registers buffers 11 Functional mode can be set Functional mode Functional mo...

Page 1272: ...nts neither the channels outputs nor the FTM counter are changed Software must select these reload points at the safe points in time 41 5 29 1 Reload Opportunities The reload opportunities are 1 At th...

Page 1273: ...he bits CNTMAX and CNTMIN according to Table 41 21 Table 41 21 Reload opportunities enabled by the bits CNTMAX and CNTMIN when the FTM counter is up down counter CNTMAX CNTMIN Reload Opportunities 0 0...

Page 1274: ...es a reload point The following figure shows an example when the LDFQ 4 0 4 4 enabled reload opportunities LDFQ 4 0 counter of the reload opportunities 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 reload point s...

Page 1275: ...the global load OK GLDOK bit in the PWMLOAD register Global load may be enabled or disabled configuring the global load enable GLEN bit in the PWMLOAD register Writing one in the GLDOK bit with GLEN e...

Page 1276: ...f GTBEEN 1 the FTM counter update is enabled only when gtb_in is 1 In the configuration described in the preceding figure FTM modules A and B have their FTM counters enabled if at least one of the gtb...

Page 1277: ...he preceding figure write 1 to CONF GTBEOUT in the FTM module used as the time base 41 5 32 Channel trigger output The channel trigger output provides a trigger signal which has one FTM input clock pe...

Page 1278: ...f this external logic The term channel n output means the channel n output value after the Polarity Control See Features Priority and Polarity Control for more details channel n output FTM module FSTA...

Page 1279: ...a free running counter when the FTM is in quadrature decoder mode 41 5 34 1 1 Up Counting When the FTM counter is an up counter and the PWM period dithering is enabled at the end of each PWM period th...

Page 1280: ...r value is MOD CNTIN 1 and the fractional value is FRACMOD 32 See the example below 0x16 0x1B 0x00 0x05 0x0A 0x0F 0x14 0x19 0x1E 0x03 0x08 0x0D 0x12 0x17 0x1C 0x01 0x06 0x0B 0x10 0x15 0x1A 0x1F 0x04 0...

Page 1281: ...D and C n 1 V MOD 1 41 5 34 1 2 Up Down Counting When the FTM counter is an up down counter and the PWM period dithering is enabled at the end of each PWM period the FRACMOD value is added to an inter...

Page 1282: ...b10 using CPWM mode and PWM Period Dithering it is recommended to use C n V 15 0 and C n V MOD 1 and MOD 0x0000 41 5 34 2 PWM Edge Dithering The channel n internal accumulator used in the PWM edge dit...

Page 1283: ...ns on the channel n match FTM counter C n V that is its position is not modified by the edge dithering However if there was the overflow of the channel n accumulator in the current EPWM period then th...

Page 1284: ...decimal are DC1 50 x T DC2 51 x T average duty cycle 50 5 32 x T 50 15625 x T PWM edge dithering PWM edge dithering PWM edge dithering PWM edge dithering PWM edge dithering Figure 41 121 Example of Av...

Page 1285: ...PWM Mode with PWM Edge Dithering 41 5 34 2 3 Combine Mode In the Combine mode the PWM edge dithering can be done in the channel n match FTM counter C n V edge or in the channel n 1 match FTM counter C...

Page 1286: ...ulator remains with the rest of the subtraction the result of this adding 0x20 If there was not the overflow of the channel n 1 accumulator in the current PWM period the channel n 1 match edge is not...

Page 1287: ...1 V edge The channel n match edge dithering is enabled when a non zero value is written to the channel n FRACVAL For the channel n match edge dithering the channel n has an internal 5 bit accumulator...

Page 1288: ...remains with the rest of the subtraction the result of this adding 0x20 If there was not the overflow of the channel n 1 accumulator in the current PWM period the channel n 1 match edge is not modifie...

Page 1289: ...n 1 FRACVAL is zero 41 6 Reset Overview The FTM is reset whenever any chip reset occurs When the FTM exits from reset the FTM counter and the prescaler counter are zero and are stopped CLKS 1 0 2 b00...

Page 1290: ...0x0010 0x0018 0x0017 XXXX 0x0000 0x0012 FTM counter CLKS 1 0 channel n output 4 write 1 to SC CLKS 3 write any value to CNT register 2 FTM configuration channel n pin is controlled by FTM NOTES CNTIN...

Page 1291: ...on to update the channel output to the zero Figure 41 128 FTM behavior after reset when the channel n is in Output Compare mode 41 7 FTM Interrupts 41 7 1 Timer Overflow Interrupt The timer overflow i...

Page 1292: ...Initialization Do not change the polarity control Do not configure the HW synchronization 4 Write any value to CNT The FTM Counter is reset and the channels outputs are updated according to new confi...

Page 1293: ...C is used SWSOC 1 and SWOC 1 then write to SWOCTRL register d If the Inverting is used SWINVC 1 and INVC 1 then write to INVCTRL register e Write to OUTMASK to enable the masked channels 7 Generate th...

Page 1294: ...Initialization Procedure MWCT101xS Series Reference Manual Rev 3 07 2019 1294 NXP Semiconductors...

Page 1295: ...lable power modes for details on available power modes Accessing LPIT when its functional clock is disabled may give transfer error 42 1 2 LPIT DMA Periodic Trigger Assignments The LPIT generates peri...

Page 1296: ...sed as an alternate ADC hardware trigger source the implementation is through TRGMUX Each LPIT channel supports one pre trigger and one trigger The LPIT channels are implemented based on independent c...

Page 1297: ...SIM_ADCOPT ADC0SWPRETRG Trigger Latching and Arbitration Unit The block depicts simplified schematic and doesn t show detailed latching See section Trigger Latching and Arbitration of ADC chapter for...

Page 1298: ...le to control when an LPIT timer channel starts For the exact module interactions see the SoC Configuration chapter in your device s hardware Reference Manual RM Interrupt Bus Clock IPS Bus Async Rese...

Page 1299: ...model comprises of a global register set common to all timer channels and registers for each timer channel that control their respective timer channels Access to these registers gets synchronized to...

Page 1300: ...rface Async Reset External Trigger Inputs per channel Sync ed Reset to all Timer channels Channel Registers AccessSynchronizer Counter Value Timeout Load Enable Sync ed External Triggers per channel T...

Page 1301: ...value 0h Version ID Register VERID 32 RO 0100_0000h 4h Parameter Register PARAM 32 RO 0000_0404h 8h Module Control Register MCR 32 RW 0000_0000h Ch Module Status Register MSR 32 W1C 0000_0000h 10h Mo...

Page 1302: ...24 23 22 21 20 19 18 17 16 R MAJOR MINOR W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R FEATURE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 42 4 1 2 3 Fields Field F...

Page 1303: ...0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R EXT_TRIG CHANNEL W Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 42 4 1 3 4 Fields Field Function 31 16 This read only field is reserved and always has the v...

Page 1304: ...b Allow timer channels to continue to run in Debug mode 2 DOZE_EN DOZE Mode Enable Bit Stops the timer channels when the device enters DOZE mode 0b Stop timer channels in DOZE mode 1b Allow timer chan...

Page 1305: ...to Current Timer Value CVALn registers and Reserved registers will always generate a transfer error NOTE There may be additional clock gating bits in your device that gate the peripheral clock to the...

Page 1306: ...n the trigger asserts the channel timer interrupt flag is set to 1 To clear a channel timer interrupt flag write logic 1 to it Writing 0 to a channel timer interrupt flag has no effect 0b Timer has no...

Page 1307: ...ld is reserved and always has the value 0 3 TIE3 Channel 3 Timer Interrupt Enable Enables interrupt generation when the Channel 3 Timer Interrupt Enable bit TIE3 is set to 1 and if the corresponding T...

Page 1308: ...1 7 1 Offset Register Offset SETTEN 14h 42 4 1 7 2 Function The Set Timer Enable register allows the simultaneous enabling of timer channels Timer channels can be enabled by either by writing 1 to Ti...

Page 1309: ...CLR_T_EN_3 0b No effect 1b Enables Timer Channel 3 2 SET_T_EN_2 Set Timer 2 Enable To enable timer channel 2 write 1 to Set Timer 2 Enable bit The Set Timer 2 Enable bit can be used in addition to the...

Page 1310: ...ot disable the counter The Set Timer 0 Enable bit will be cleared when Timer Enable bit TCTRL0 T_EN is set to 0 or when 1 is written to the Clear Timer 0 Enable bit CLRTEN CLR_T_EN_0 0b No effect 1b E...

Page 1311: ...Timer Channel 3 2 CLR_T_EN_2 Clear Timer 2 Enable To disable timer channel 2 write 1 to Clear Timer 2 Enable bit The Clear Timer 2 Enable bit can be used in addition to Timer Enable bit T_EN in TCTRL...

Page 1312: ...b Clear the Timer Enable bit TCTRL0 T_EN for Timer Channel 0 42 4 1 9 Timer Value Register TVAL0 TVAL3 42 4 1 9 1 Offset Register Offset TVAL0 20h TVAL1 30h TVAL2 40h TVAL3 50h 42 4 1 9 2 Function In...

Page 1313: ...lue will be loaded after the timer expires To abort the current timer cycle and start a timer period with a new value the timer channel must be disabled and enabled again In capture mode whenever the...

Page 1314: ...1 20 19 18 17 16 R TMR_CUR_VAL W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TMR_CUR_VAL W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 42 4 1 10 4 Fields Field Functio...

Page 1315: ...ger TSOT Timer Operation Mode MODE Chain Channel CHAIN There are 2 ways to disable a timer write 1 to the specific timer s Clear Timer Enable register bit CLRTEN CLR_T_EN_n or set the timer enable bit...

Page 1316: ...0b Timer will not reload on the selected trigger 1b Timer will reload on the selected trigger 17 TSOI Timer Stop On Interrupt Controls whether the channel timer will stop after it the channel timer t...

Page 1317: ...nnel timer runs independently 1b Channel Chaining is enabled The timer decrements on the previous channel s timeout 0 T_EN Timer Enable Enables or disables the Timer Channel 0b Timer Channel is disabl...

Page 1318: ...elect Trigger sources Timer enables Timer Reload on Trigger Timer Stop on Interrupt Timer Start on Trigger Device Identifiers or Trigger Accumulator or Trigger Input Capture 1 2 3 4 5 Load a Read star...

Page 1319: ...able a timer write 1 to the specific timer s Clear Timer Enable register bit CLRTEN CLR_T_EN_n or set the timer enable bit TCTRLn T_EN 0 for that channel 4 Configure the channels that are to be chaine...

Page 1320: ...re the inverse of the current counter value in the timer value register which will set the timer interrupt flag and assert the output pre trigger The timer operation is controlled by Trigger Control b...

Page 1321: ...ers are ignored until the counter times out 0 then the counter decrements immediately on the next clock edge When channel is Chained or in Capture mode TSOT has no effect In different timer modes thes...

Page 1322: ...channel behavior across several clock cycles Table 42 7 Timing diagrams list Mode Timing Diagram TSOT TROT TSOI CHAIN 32 bit periodic counter compare mode 00 Figure 42 5 0 0 0 0 Figure 42 6 0 0 1 0 F...

Page 1323: ...igure 42 5 Case 1 TSOT 0 TROT 0 TSOI 0 CHAIN 0 Mode00Case2 svg Case 2 TSOT 0 TROT 0 TSOI 1 CHAIN 0 Operation In Mode 00 the counter will load and then decrement down to zero The counter will next set...

Page 1324: ...ure 42 7 Case 3 TSOT 0 TROT 1 TSOI 0 CHAIN 0 Mode00Case4 svg Case 4 TSOT 0 TROT 1 TSOI 1 CHAIN 0 Operation In Mode 00 the counter will load and then decrement down to zero The counter will next set th...

Page 1325: ...de00Case6 svg Case 6 TSOT 1 TROT 0 TSOI 1 CHAIN 0 Operation In Mode 00 the counter will load and then decrement down to zero The counter will next set the timer interrrupt flag and assert the output p...

Page 1326: ...will load and then decrement down to zero The counter will next set the timer interrrupt flag and assert the output pre trigger T_EN 0xFFFF_FFFF TMR_VAL TMR_CUR_VAL 0x0000_0000 IN_TRIG PRE_TRIG_OUT TR...

Page 1327: ...out Countdown is based on the selected clock TMR_VAL_L 0x0000 0xFFFF TMR_CUR_VAL Mode 01 16 bit Dual Compare Mode Periodic Counter Figure 42 13 Case 1 TSOT 0 TROT 0 TSOI 0 CHAIN 0 Effect of Timer Cont...

Page 1328: ...out assertion a timeout is asserted The timer does not start counting again until a new trigger s rising edge is detected Similar to Figure 42 10 1 1 0 For repeated interrupts with reload timer mode O...

Page 1329: ...tput pre trigger and trigger T_EN IN_TRIG PRE_TRIG_OUT TRIG_OUT Countdown is based on the selected clock TSOT X TROT X TSOI 0 CHAIN 0 Timer resets when T_EN 0 1 clock TMR_CUR_VAL 2 clocks 0xFFFF_FFFF...

Page 1330: ...MR_VAL 0x0000_0000 Timer reloads on trigger after timeout and decrements on subsequent triggers Timer loads on 1st trigger and decrements on subsequent triggers In Mode 10 the counter will load on the...

Page 1331: ...T Countdown is based on the selected clock TSOT X TROT 0 TSOI 0 CHAIN 0 Timer resets when T_EN 0 set the timer interrupt flag 1 clock 2 clocks 0xFFFF_FFFF TMR_CUR_VAL 0x0000_0000 and assert the output...

Page 1332: ...ntdown is based on the selected clock TSOT X TROT 1 TSOI 0 CHAIN 0 Timer resets when T_EN 0 set the timer interrupt flag 1 clock 2 clocks 0xFFFF_FFFF TMR_CUR_VAL 0x0000_0000 and assert the output pre...

Page 1333: ...F_FFFF TMR_CUR_VAL 0x0000_0000 and assert the output pre trigger and trigger TMR_VAL read value Timer stops after timer interrrupt TMR_VAL is in TVALn register TMR_CUR_VAL is in CVALn register 0xFFFF_...

Page 1334: ...n be chained It is preferred to have the same trigger source and timer controls 0xFFFF TMR_VAL 0x0000 PRE_TRIG_OUT TRIG_OUT TMR_VAL 0xFFFF 0x0000 PRE_TRIG_OUT TRIG_OUT Timer n Timer n Timer n 1 Timer...

Page 1335: ...mode and Wait mode are not supported in this device See Module operation in available power modes for details on available power modes For LPTMR_PSR PCS bit options refer to table Peripheral module c...

Page 1336: ...bit time counter or pulse counter with compare Optional interrupt can generate asynchronous wakeup from any low power mode Hardware trigger output Counter supports free running mode or reset on compar...

Page 1337: ...iptions Table 43 4 LPTMR interface detailed signal descriptions Signal I O Description LPTMR_ALTn I Pulse Counter Input The LPTMR can select one of the input pins to be used in Pulse Counter mode Stat...

Page 1338: ...000_0000h Ch Low Power Timer Counter Register CNR 32 RW 0000_0000h 43 4 1 2 Low Power Timer Control Status Register CSR 43 4 1 2 1 Offset Register Offset CSR 0h 43 4 1 2 2 Diagram Bits 31 30 29 28 27...

Page 1339: ...nter input 1 is selected 10b Pulse counter input 2 is selected 11b Pulse counter input 3 is selected 3 TPP Timer Pin Polarity Configures the polarity of the input source in Pulse Counter mode TPP must...

Page 1340: ...ter does not support this configuration 0001b Prescaler divides the prescaler clock by 4 glitch filter recognizes change on input pin after 2 rising clock edges 0010b Prescaler divides the prescaler c...

Page 1341: ...clock by 65 536 glitch filter recognizes change on input pin after 32 768 rising clock edges 2 PBYP Prescaler Bypass When PBYP is set the selected prescaler clock in Time Counter mode or selected inp...

Page 1342: ...is enabled and the CNR equals the value in the CMR and increments TCF is set and the hardware trigger asserts until the next time the CNR increments If the CMR is 0 the hardware trigger will remain a...

Page 1343: ...to remain operating during a low power mode then it must be disabled before entering the mode The LPTMR is reset only on global Power On Reset POR or Low Voltage Detect LVD When configuring the LPTMR...

Page 1344: ...Counter mode and as a glitch filter in Pulse Counter mode NOTE The prescaler glitch filter configuration must not be altered when the LPTMR is enabled 43 5 3 1 Prescaler enabled In Time Counter mode w...

Page 1345: ...ne or two prescaler clock edges due to synchronization logic 43 5 3 4 Glitch filter bypassed In Pulse Counter mode when the glitch filter is bypassed the selected input source increments the CNR every...

Page 1346: ...he CMR must be written and CSR TCF must be cleared before the LPTMR counter has incremented past the new LPTMR compare value NOTE When the LPTMR is enabled in Time Counter mode the first increment wil...

Page 1347: ...is always enabled When Then The CMR is set to 0 with CSR TFC clear The LPTMR hardware trigger will assert on the first compare and does not deassert The CMR is set to a nonzero value or if CSR TFC is...

Page 1348: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 1348 NXP Semiconductors...

Page 1349: ...or can be configured by software NOTE There is no internal 32 768 kHz crystal oscillator available on this device All references to 32 768 kHz clock in this chapter refers to RTC_CLK See RTC clocking...

Page 1350: ...0 12 ppm and 3906 ppm Option to increment prescaler using a 1 kHz LPO prescaler increments by 32 every clock edge Register write protection Lock register requires POR or software reset to enable write...

Page 1351: ...register protected by the lock register does not generate a bus error but the write will not complete 44 3 1 RTC register descriptions 44 3 1 1 RTC Memory map RTC base address 4003_D000h Offset Regis...

Page 1352: ...increments once a second provided SR TOF or SR TIF are not set The time counter will read as zero when SR TOF or SR TIF are set When the time counter is disabled the TSR can be read or written Writing...

Page 1353: ...e time counter is enabled the TPR is read only and increments every 32 768 kHz clock cycle The time counter will read as zero when SR TOF or SR TIF are set When the time counter is disabled the TPR ca...

Page 1354: ...TAF is set whenever the TAR TAR equals the TSR TSR and the TSR TSR increments Writing to the TAR clears the SR TAF 44 3 1 5 RTC Time Compensation Register TCR 44 3 1 5 1 Offset Register Offset TCR Ch...

Page 1355: ...e value written should be one less than the number of seconds For example write zero to configure for a compensation interval of one second This register is double buffered and writes do not take affe...

Page 1356: ...Reserved UM SU P Reserved SW R W 0 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44 3 1 6 3 Fields Field Function 31 26 Reserved 25 Reserved 24 CPE Clock Pin Enable 0b The RTC_CLKOUT function...

Page 1357: ...tput on RTC_CLKOUT 1b The RTC 32 768 kHz clock is output on RTC_CLKOUT provided it is output to other peripherals 4 Reserved 3 UM Update Mode Allows SR TCE to be written even when the Status Register...

Page 1358: ...he TAR TAR equals the TSR TSR and the TSR TSR increments This bit is cleared by writing the TAR register 0b Time alarm has not occurred 1b Time alarm has occurred 1 TOF Time Overflow Flag Time overflo...

Page 1359: ...Field Function 31 8 Reserved 7 Reserved 6 LRL Lock Register Lock After being cleared this bit can be set only by POR or software reset 0b Lock Register is locked and writes are ignored 1b Lock Regist...

Page 1360: ...ation Register is not locked and writes complete as normal 2 0 Reserved 44 3 1 9 RTC Interrupt Enable Register IER 44 3 1 9 1 Offset Register Offset IER 1Ch 44 3 1 9 2 Diagram Bits 31 30 29 28 27 26 2...

Page 1361: ...equency of the seconds interrupt is configured by TSIC 0b Seconds interrupt is disabled 1b Seconds interrupt is enabled 3 Reserved 2 TAIE Time Alarm Interrupt Enable 0b Time alarm flag does not genera...

Page 1362: ...and must be cleared by software 44 4 1 3 Supervisor access When the supervisor access control bit is clear only supervisor mode software can write to the RTC registers non supervisor mode software wi...

Page 1363: ...as high as 3906 ppm and as low as 0 12 ppm The compensation factor must be calculated externally to the RTC and supplied by software to the compensation register The RTC itself does not calculate the...

Page 1364: ...R This will usually be the next alarm value although writing a value that is less than TSR such as 0 will prevent SR TAF from setting again SR TAF cannot otherwise be disabled although the interrupt i...

Page 1365: ...om any low power mode The RTC seconds interrupt is an edge sensitive interrupt with a dedicated interrupt vector that is generated once a second and requires no software overhead there is no correspon...

Page 1366: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 1366 NXP Semiconductors...

Page 1367: ...ariant See tab PeripheralSummaries of IO Signal Description Input Multiplexing sheet attached to the Reference Manual for information on available chip selects The exact number of chip selects for eac...

Page 1368: ...vailable NOTE The Serial Peripheral Interface bus SPI is a synchronous serial communication interface used in embedded systems typically to perform short distance communications between microcontrolle...

Page 1369: ...r combinations of crossbar switches NICs and similar modules Secure digital cards Ethernet USB CAN MMC SD SDIO displays LCD USART temperature Figure 45 3 Typical LPSPI connection scheme SPI accesses a...

Page 1370: ...es Support for full duplex transfers supporting 1 bit transmit and receive on each clock edge Support for half duplex transfers supporting 1 bit transmit or receive on each clock edge Support for half...

Page 1371: ...e wire SPI Interface Peripheral Bus External Figure 45 4 Block Diagram 45 2 3 Modes of operation Table 45 2 Chip modes supported by the LPSPI module Chip mode LPSPI Operation Run Normal operation Stop...

Page 1372: ...ansmit transfers I O PCS 3 DATA 3 Peripheral Chip Select or data pin 3 during quad data transfers Input in slave mode Output in master mode Input in quad data receive transfers Output in quad data tra...

Page 1373: ...ster has a separate slave select pin for each slave its own separately wired slave select line 3 independent SPI slaves Slaves are considered Typical SPI bus scheme independent of each other Figure 45...

Page 1374: ...vice can support 1 slave select line pin for multiple slaves data flow from master device to slave devices Master sends data directly to the slave that the data is for the slaves for whom the data is...

Page 1375: ...RW 0000_0000h 24h Configuration Register 1 CFGR1 32 RW 0000_0000h 30h Data Match Register 0 DMR0 32 RW 0000_0000h 34h Data Match Register 1 DMR1 32 RW 0000_0000h 40h Clock Configuration Register CCR...

Page 1376: ...rsion number for the module specification Read only field 23 16 MINOR Minor Version Number Returns the minor version number for the module specification Read only field 15 0 FEATURE Module Identificat...

Page 1377: ...d Function 31 24 Reserved 23 16 Reserved 15 8 RXFIFO Receive FIFO Size Sets the maximum number of words in the receive FIFO which is 2RXFIFO 7 0 TXFIFO Transmit FIFO Size Sets the maximum number of wo...

Page 1378: ...bit should be updated only when the LPSPI module is disabled 0b LPSPI module is disabled in debug mode 1b LPSPI module is enabled in debug mode 2 DOZEN Doze Mode Enable Enables or disables the LPSPI...

Page 1379: ...ch Flag Indicates that the received data has matched the MATCH0 and or MATCH1 fields as configured by CFGR1 MATCFG Configuration Register 1 0b Have not received matching data 1b Have received matching...

Page 1380: ...S negates 0b Frame transfer has not completed 1b Frame transfer has completed 8 WCF Word Complete Flag The Word Complete Flag will set when the last bit of a received word is sampled 0b Transfer of a...

Page 1381: ...eceive Error Interrupt Enable 0b Disabled 1b Enabled 11 TEIE Transmit Error Interrupt Enable 0b Disabled 1b Enabled 10 TCIE Transfer Complete Interrupt Enable 0b Disabled 1b Enabled 9 FCIE Frame Compl...

Page 1382: ...TDDE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 45 3 1 7 3 Fields Field Function 31 2 Reserved 1 RDDE Receive Data DMA Enable 0b DMA request is disabled 1b DMA request is enabled 0 TDDE Transmit Data DM...

Page 1383: ...eived data is discarded unless the Data Match Flag DMF is set 8 CIRFIFO Circular FIFO Enable When enabled the transmit FIFO read pointer is saved to a temporary register The transmit FIFO will be empt...

Page 1384: ...r Offset CFGR1 24h 45 3 1 9 2 Function The CFGR1 should only be written when the LPSPI is disabled 45 3 1 9 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 PCSCF G OUTCFG PINCFG 0 M...

Page 1385: ...ord equals MATCH0 OR MATCH1 i e 1st data word MATCH0 MATCH1 011b 011b Match is enabled if any data word equals MATCH0 OR MATCH1 i e any data word MATCH0 MATCH1 100b 100b Match is enabled if 1st data w...

Page 1386: ...ster mode the Automatic PCS bit is ignored 0b Automatic PCS generation is disabled 1b Automatic PCS generation is enabled 1 SAMPLE Sample Point When set the LPSPI master will sample the input data on...

Page 1387: ...y CFGR0 RDMO is enabled the Match 0 Value is compared against the received data 45 3 1 11 Data Match Register 1 DMR1 45 3 1 11 1 Offset Register Offset DMR1 34h 45 3 1 11 2 Diagram Bits 31 30 29 28 27...

Page 1388: ...ation Register cannot be changed when the LPSPI is enabled 45 3 1 12 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R SCKPCS PCSSCK W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 1...

Page 1389: ...between the PCS negation of the last transfer and PCS assertion of the next transfer The command word sets which PCS signal is used of PCS 3 0 the polarity phase of the SCK signal and the Prescaler V...

Page 1390: ...never the number of words in the receive FIFO is greater than RXWATER Writing a value equal or greater than the FIFO size will be truncated 15 8 Reserved 7 2 Reserved 1 0 TXWATER Transmit FIFO Waterma...

Page 1391: ...24 Reserved 23 19 Reserved 18 16 RXCOUNT Receive FIFO Count Returns the number of words currently stored in the receive FIFO 15 8 Reserved 7 3 Reserved 2 0 TXCOUNT Transmit FIFO Count Returns the num...

Page 1392: ...l then update The command word can be changed during a continuous transfer if CONTC of the new command word is set and the command word is written on a frame size boundary In slave mode the command wo...

Page 1393: ...ated between frames 00b Transfer using LPSPI_PCS 0 01b Transfer using LPSPI_PCS 1 10b Transfer using LPSPI_PCS 2 11b Transfer using LPSPI_PCS 3 23 LSBF LSB First 0b Data is transferred MSB first 1b Da...

Page 1394: ...hardware at the end of the transfer 0b Normal transfer 1b Mask transmit data 17 16 WIDTH Transfer Width For 2 bit or 4 bit transfers either Receive Data Mask RXMSK or Transmit Data Mask TXMSK must be...

Page 1395: ...0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W DATA Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 45 3 1 16 4 Fields Field Function 31 0 DATA Transmit Data Both 8 bit and 16 bit writes of transmit data w...

Page 1396: ...rved 1 RXEMPTY RX FIFO Empty 0b RX FIFO is not empty 1b RX FIFO is empty 0 SOF Start Of Frame Indicates that this is the first data word received after LPSPI_PCS assertion 0b Subsequent data word rece...

Page 1397: ...uency must be at least 2 times faster than the SPI external clock frequency LPSPI_SCK External clock The LPSPI shift register is clocked directly by the LPSPI_SCK clock How the LPSPI_SCK clock is gene...

Page 1398: ...mmand word is pulled from the FIFO and that command word controls all subsequent transfers If LPSPI is busy and the Continuous Transfer bit TCR CONT is set or cleared and the Continuing Command bit TC...

Page 1399: ...PI bus transfer unless the Transmit Data Mask TCR TXMSK bit is set When the Transmit Data Mask bit is set a new command word will not be loaded until the end of the existing frame based on FRAMESZ con...

Page 1400: ...d during receive data matching Y TXMSK Transmit Data Mask Masks the transmit data so that masked transmit data is not pulled from transmit FIFO and the output data pin is tristated unless configured b...

Page 1401: ...e circular FIFO mode is enabled 45 4 2 2 Receive FIFO and Data Match The receive FIFO is used to store receive data during SPI bus transfers When the Receive Data Mask TCR RXMSK bit is set the receive...

Page 1402: ...When SCK Divider is configured to an odd number of cycles the first half of the LPSPI_SCK cycle is one cycle longer than the second half of the LPSPI_SCK cycle 0 2 cycles 255 257 cycles DBT Delay Betw...

Page 1403: ...ig CFGR1 OUTCFG When performing quad data transfers the Peripheral Chip Select Configuration CFGR1 PCSCFG must be enabled The Peripheral Chip Select Configuration CFGR1 PCSCFG is also used to disable...

Page 1404: ...it and Command FIFO commands Before enabling the LPSPI in slave mode the Transmit Command Register TCR should be initialized although the Transmit Command Register register will not update until after...

Page 1405: ...output data pin is tristated unless configured by Output Config CFGR1 OUTCFG Useful for half duplex transfers WIDTH Transfer Width Configures the number of bits shifted on each LPSPI_SCK pulse 1 bit t...

Page 1406: ...module supports interfacing to external masters that provide only clock and data pins LPSPI_PCS is not required This interface requires using Clock Phase TCR CPHA 1 data is changed on the leading edg...

Page 1407: ...empty or receive FIFO is full the Transmit Error Flag bit cannot set Y N Y REF Receive Error Flag Receive error flag indicates a receive FIFO overflow In master mode when the No Stall CFGR1 NOSTALL b...

Page 1408: ...LPSPI bus transfer the LPSPI input trigger can be selected instead of the LPSPI_HREQ input The LPSPI input trigger is synchronized and must assert for at least 2 cycles of the LPSPI functional clock d...

Page 1409: ...T1016S LPI2C0 4 4 Yes Yes LPI2C1 4 4 Yes Yes Low leakage and Wait mode is not supported in this device See Module operation in available power modes for details on available power modes HS Mode baud r...

Page 1410: ...plus and ultra fast modes of operation The LPI2C is designed to use little CPU overhead with DMA offloading of FIFO register accesses The LPI2C can continue operating in stop modes if an appropriate c...

Page 1411: ...nal peripherals that use an I C bus Many devices can be connected to the I C bus but only 1 device can be accessed at a time or Asynchronous Bus Fabric Bus fabric can be crossbar switches NICs or comb...

Page 1412: ...s before initiating transfer Command FIFO can initiate repeated START and STOP conditions and one or more master receiver transfers STOP condition can be generated from command FIFO or generated autom...

Page 1413: ...block diagram 46 2 3 Modes of operation Table 46 2 Chip modes supported by the LPI2C module Chip mode LPI2C Operation Run Normal operations Stop Can continue operating in stop mode if the Doze Enable...

Page 1414: ...t pin If LPI2C master slave are configured to use separate pins then this the LPI2C slave SDA pin I O 46 2 5 Wiring options LPI2C can be used to implement 2 wire or 4 wire I2C serial busses Printed Ci...

Page 1415: ...6 4 Wire scheme 46 3 Memory Map and Registers NOTE Writing a Read Only RO register or reading a Write Only WO register can cause bus errors This module will not check if programmed values in the regi...

Page 1416: ...R0 32 RW 0000_0000h 50h Master Clock Configuration Register 1 MCCR1 32 RW 0000_0000h 58h Master FIFO Control Register MFCR 32 RW 0000_0000h 5Ch Master FIFO Status Register MFSR 32 RO 0000_0000h 60h Ma...

Page 1417: ...JOR Major Version Number Returns the major version number for the module design specification Read only field 23 16 MINOR Minor Version Number Returns the minor version number for the module design sp...

Page 1418: ...0 R 0 MRXFIFO 0 MTXFIFO W Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 46 3 1 3 4 Fields Field Function 31 16 Reserved 15 12 Reserved 11 8 MRXFIFO Master Receive FIFO Size Configures the number of words in t...

Page 1419: ...10 Reserved 9 RRF Reset Receive FIFO 0b No effect 1b Receive FIFO is reset 8 RTF Reset Transmit FIFO 0b No effect 1b Transmit FIFO is reset 7 4 Reserved 3 DBGEN Debug Enable 0b Master is disabled in d...

Page 1420: ...14h 46 3 1 5 2 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 BBF MBF 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 DMF PLT F FE F ALF NDF...

Page 1421: ...eceiving data without a START condition 11 ALF Arbitration Lost Flag Set if the LPI2C master transmits a logic one and detects a logic zero on the I2C bus or if the LPI2C master detects a START or STO...

Page 1422: ...mit FIFO is equal or less than TXWATER 0b Transmit data is not requested 1b Transmit data is requested 46 3 1 6 Master Interrupt Enable Register MIER 46 3 1 6 1 Offset Register Offset MIER 18h 46 3 1...

Page 1423: ...t Enable 0b Disabled 1b Enabled 9 SDIE STOP Detect Interrupt Enable 0b Disabled 1b Enabled 8 EPIE End Packet Interrupt Enable 0b Disabled 1b Enabled 7 2 Reserved 1 RDIE Receive Data Interrupt Enable 0...

Page 1424: ...0 0 46 3 1 7 3 Fields Field Function 31 2 Reserved 1 RDDE Receive Data DMA Enable 0b DMA request is disabled 1b DMA request is enabled 0 TDDE Transmit Data DMA Enable 0b DMA request is disabled 1b DMA...

Page 1425: ...r the LPI2C master is idle and the transmit FIFO is empty then the read pointer value will be restored from the temporary register This will cause the contents of the transmit FIFO to be cycled throug...

Page 1426: ...CFGR1 24h 46 3 1 9 2 Function The MCFGR1 should only be written when the I2C Master is disabled 46 3 1 9 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 PINCFG 0 MATCFG W Reset 0...

Page 1427: ...in push pull mode with separate LPI2C slave 111b 4 pin push pull mode inverted outputs 23 19 Reserved 18 16 MATCFG Match Configuration Configures the condition that will cause the DMF to set 000b Matc...

Page 1428: ...PI2C master is busy 7 3 Reserved 2 0 PRESCALE Prescaler Configures the clock prescaler used for all LPI2C master logic except for the digital glitch filters 000b Divide by 1 001b Divide by 2 010b Divi...

Page 1429: ...h Speed mode 23 20 Reserved 19 16 FILTSCL Glitch Filter SCL Configures the I2C master digital glitch filters for SCL input A configuration of 0 will disable the glitch filter Glitches equal to or less...

Page 1430: ...2 11 10 9 8 7 6 5 4 3 2 1 0 R PINLOW 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 46 3 1 11 4 Fields Field Function 31 20 Reserved 19 8 PINLOW Pin Low Timeout Configures the pin low timeout flag in clock...

Page 1431: ...4 3 2 1 0 R 0 MATCH0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 46 3 1 12 4 Fields Field Function 31 24 Reserved 23 16 MATCH1 Match 1 Value Compared against the received data when receive data match is e...

Page 1432: ...mber of cycles minus one that is used as the data hold time for SDA Must be configured less than the minimum SCL low period 23 22 Reserved 21 16 SETHOLD Setup Hold Delay Minimum number of cycles minus...

Page 1433: ...onal board delay due to external loading this time is equal to 2 FILTSCL 2 PRESCALE cycles 46 3 1 14 Master Clock Configuration Register 1 MCCR1 46 3 1 14 1 Offset Register Offset MCCR1 50h 46 3 1 14...

Page 1434: ...ock High Period Minimum number of cycles minus one that the SCL clock is driven high by the master The SCL high time is extended by the time it takes to detect a rising edge on the external SCL pin Ig...

Page 1435: ...ive FIFO Watermark The Receive Data Flag is set whenever the number of words in the receive FIFO is greater than RXWATER Writing a value equal to or greater than the FIFO size will be truncated 15 2 R...

Page 1436: ...ceive FIFO Count Returns the number of words in the receive FIFO 15 3 Reserved 2 0 TXCOUNT Transmit FIFO Count Returns the number of words in the transmit FIFO 46 3 1 17 Master Transmit Data Register...

Page 1437: ...a 000b Transmit DATA 7 0 001b Receive DATA 7 0 1 bytes 010b Generate STOP condition 011b Receive and discard DATA 7 0 1 bytes 100b Generate repeated START and transmit address in DATA 7 0 101b Generat...

Page 1438: ...Function 31 15 Reserved 14 RXEMPTY RX Empty 0b Receive FIFO is not empty 1b Receive FIFO is empty 13 8 Reserved 7 0 DATA Receive Data Reading the Receive Data register returns the data received by th...

Page 1439: ...ffect 1b Transmit Data Register is now empty 7 6 Reserved 5 FILTDZ Filter Doze Enable Filter Doze Enable bit should only be updated when the I2C Slave is disabled 0b Filter remains enabled in Doze mod...

Page 1440: ...R 0 BBF SBF 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SAR F GCF AM1F AM0F FE F BE F SD F RS F 0 TAF AVF RD F TDF W W1C W1C W1C W1C Reset 0 0 0 0 0 0 0 0 0...

Page 1441: ...ss 1b Have received an ADDR1 or ADDR0 ADDR1 range matching address 12 AM0F Address Match 0 Flag Indicates that the received address has matched the ADDR0 field as configured by ADDRCFG Address Match 0...

Page 1442: ...by reading the Receive Data register 0b Address Status Register is not valid 1b Address Status Register is valid 1 RDF Receive Data Flag Receive Data Flag is cleared by reading the receive data regis...

Page 1443: ...able 0b Disabled 1b Enabled 13 AM1F Address Match 1 Interrupt Enable 0b Disabled 1b Enabled 12 AM0IE Address Match 0 Interrupt Enable 0b Enabled 1b Disabled 11 FEIE FIFO Error Interrupt Enable 0b Disa...

Page 1444: ...Register Offset SDER 11Ch 46 3 1 22 2 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 AVDE RDD...

Page 1445: ...quest is disabled 1b DMA request is enabled 46 3 1 23 Slave Configuration Register 1 SCFGR1 46 3 1 23 1 Offset Register Offset SCFGR1 124h 46 3 1 23 2 Function The Slave Configuration Register 1 shoul...

Page 1446: ...F 1b Reading the Receive Data register when the Address Valid flag SSR AVF is set will return the Address Status register and clear the Address Valid flag Reading the Receive Data register when the Ad...

Page 1447: ...er Clock stretching occurs following the 9th bit and is therefore compatible with high speed mode 0b Clock stretching is disabled 1b Clock stretching is enabled 1 RXSTALL RX SCL Stall Enables SCL cloc...

Page 1448: ...TSCL Glitch Filter SCL Configures the I2C slave digital glitch filters for SCL input A configuration of 0 will disable the glitch filter Glitches equal to or less than FILTSCL cycles long will be filt...

Page 1449: ...140h 46 3 1 25 2 Function The SAMR should only be written when the I2C Slave is disabled 46 3 1 25 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 ADDR1 0 W Reset 0 0 0 0 0 0 0 0 0...

Page 1450: ...address byte is compared to ADDR0 8 1 In 7 bit mode the address is compared to ADDR0 7 1 0 Reserved 46 3 1 26 Slave Address Status Register SASR 46 3 1 26 1 Offset Register Offset SASR 150h 46 3 1 26...

Page 1451: ...r STAR 46 3 1 27 1 Offset Register Offset STAR 154h 46 3 1 27 2 Function The Slave Transmit ACK Register can only be written when the ACK SCL Stall bit is set in Slave Configuration Register 1 SCFGR1...

Page 1452: ...set a Transmit NACK must be written once for each matching address byte and each received word ACKSTALL must be set because that will stall the data transfer until software reads the received word and...

Page 1453: ...d TXDSTALL 0 then the transmit data should be written before the start of the slave transmit transfer otherwise i e if the transmit data is not written before the start of the slave transmit transfer...

Page 1454: ...tart Of Frame 0b Indicates this is not the first data word since a repeated START or STOP condition 1b Indicates this is the first data word since a repeated START or STOP condition 14 RXEMPTY RX Empt...

Page 1455: ...s for the LPI2C master and slave are reset to their default state on a chip reset Software reset The LPI2C master implements a software reset bit in its Control Register The MCR RST will reset all mas...

Page 1456: ...ith the master transmit data A START or Repeated START condition that is expecting a NACK for example HS mode master code must be followed by a STOP or repeated START condition 46 4 2 2 Master operati...

Page 1457: ...iscarded due to command or receive data match and the receive FIFO is full 46 4 2 3 Receive FIFO and Data Matching The receive FIFO is used to store receive data during master receiver transfers Recei...

Page 1458: ...I 1 SCL_LATENCY x 2 PRESCALE setup time for a repeated START condition or STOP condition tSU STA tSU STO SETHOLD 1 SCL_LATENCY x 2 PRESCALE data hold time tHD DAT DATAVD 1 x 2 PRESCALE data setup time...

Page 1459: ...reater than CLKHI 1 The timing parameters must be configured to meet the requirements of the I2C specification this will depend on the mode being supported and the LPI2C functional clock frequency Whe...

Page 1460: ...e used to force the I2C bus to be considered idle when SCL and SDA remain high for BUSIDLE 1 prescaler cycles The I2C bus is normally considered idle when the LPI2C master is first enabled but when BU...

Page 1461: ...e configuration the LPI2C master logic and LPI2C slave logic are not able to connect to separate I2C buses 46 4 3 Slave Mode To perform all slave mode transfers on the I2C bus the LPI2C slave logic op...

Page 1462: ...g the 9th clock pulse of the address byte and the Address Valid flag is set During the 9th clock pulse of a slave transmit transfer and the Transmit Data flag is set During the 9th clock pulse of a sl...

Page 1463: ...retching FIFO error flag will also set due to an address overrun when RXCFG is set otherwise an address overrun is not flagged To eliminate the possibility of overrun occurring enable clock stretching...

Page 1464: ...etected at the wrong time Or the master was transmitting data but received different data than the data that was transmitted Y N Y FEF FIFO Error Flag The master is expecting a START condition in the...

Page 1465: ...a than what was transmitted Y N Y FEF FIFO Error Flag Transmit data underrun Receive data overrun Address status overrun when Receive Data Configuration SCFGR1 RXCFG 1 FEF flag can only set when clock...

Page 1466: ...an output trigger that can be connected to other peripherals on the device The slave output trigger asserts on both a Repeated START or STOP condition that occurs after a slave address match and the...

Page 1467: ...able 47 1 LPUART instances and features Chip Instances TX FIFO word RX FIFO word WCT1014S LPUART0 4 4 LPUART1 4 4 LPUART2 4 4 WCT1015S LPUART0 4 4 LPUART1 4 4 LPUART2 4 4 WCT1016S LPUART0 4 4 LPUART1...

Page 1468: ...receive pin Break detect supporting LIN Receive data match Hardware parity generation and checking Programmable 7 bit 8 bit 9 bit or 10 bit character length Programmable 1 bit or 2 bit stop bits Three...

Page 1469: ...to cause a wakeup from Stop mode If the LPUART is disabled in Stop mode then it can generate a wakeup via the STAT RXEDGIF flag if the receiver detects an active edge 47 2 2 2 Debug mode The LPUART r...

Page 1470: ...TxD TxD Direction TO TxD Pin Logic Loop Control To Receive Data In To TxD Pin Tx Interrupt Request LOOPS RSRC TIE TC TDRE M PT PE TCIE TE SBK T8 TXDIR Load From LPUARTx_D TXINV BRK13 ASYNCH MODULE CLO...

Page 1471: ...includes registers to control baud rate select options report status and store transmit receive data Access to an address outside the valid memory map will generate a bus error NOTE Writing a Read On...

Page 1472: ...0C0_0000h 18h LPUART Control Register CTRL 32 RW 0000_0000h 1Ch LPUART Data Register DATA 32 RW 0000_1000h 20h LPUART Match Address Register MATCH 32 RW 0000_0000h 24h LPUART Modem IrDA Register MODIR...

Page 1473: ...ead only field returns the minor version number for the module specification 15 0 FEATURE Feature Identification Number This read only field returns the feature set number 0000000000000001b Standard f...

Page 1474: ...0 0 0 0 0 1 0 47 3 1 3 4 Fields Field Function 31 16 Reserved 15 8 RXFIFO Receive FIFO Size The number of words in the receive FIFO is 2 RXFIFO 7 0 TXFIFO Transmit FIFO Size The number of words in the...

Page 1475: ...ction 31 2 Reserved 1 RST Software Reset Resets all internal logic and registers except the Global Register Remains set until cleared by software 0b Module is not reset 1b Module is reset 0 Reserved 4...

Page 1476: ...field should only be changed when the transmitter and receiver are both disabled 00b Input trigger is disabled 01b Input trigger is used instead of RXD pin input 10b Input trigger is used instead of C...

Page 1477: ...ansmitter use 10 bit data characters 28 24 OSR Oversampling Ratio This field configures the oversampling ratio for the receiver This field should only be changed when the transmitter and receiver are...

Page 1478: ...00_33FF and does not pull data from the FIFO 0b DMA request disabled 1b DMA request enabled 19 18 MATCFG Match Configuration Configures the match addressing mode used This field should only be changed...

Page 1479: ...when STAT RXEDGIF flag is 1 13 SBNS Stop Bit Number Select SBNS determines whether data characters have one or two stop bits This bit should only be changed when the transmitter and receiver are both...

Page 1480: ...rses the order of the bits that are transmitted and received on the wire This bit does not affect the polarity of the bits the location of the parity bit or the location of the start or stop bits This...

Page 1481: ...RXD input not idle 23 TDRE Transmit Data Register Empty Flag When the transmit FIFO is enabled TDRE will set when the number of datawords in the transmit FIFO DATA register is equal to or less than t...

Page 1482: ...verflows the buffer and all the other error flags FE NF and PF are prevented from setting The data in the shift register is lost but the data already in the LPUART data registers is not affected If LB...

Page 1483: ...fset Register Offset CTRL 18h 47 3 1 8 2 Function This read write register controls various optional features of the LPUART system This register should only be altered when the transmitter and receive...

Page 1484: ...en the LPUART is configured for single wire half duplex operation LOOPS RSRC 1 this bit determines the direction of data at the TXD pin When clearing TXDIR the transmitter will finish receiving the cu...

Page 1485: ...the current character if any 0b Receiver disabled 1b Receiver enabled 17 RWU Receiver Wakeup Control This field can be set to place the LPUART receiver in a standby state RWU automatically clears whe...

Page 1486: ...oop mode or single wire mode where transmitter outputs are internally connected to receiver input see RSRC bit 6 DOZEEN Doze Enable 0b LPUART is enabled in Doze mode 1b LPUART is disabled in Doze mode...

Page 1487: ...is enabled the bit immediately before the stop bit is treated as the parity bit 0b No hardware parity generation or checking 1b Parity enabled 0 PT Parity Type Provided parity is enabled PE 1 this bi...

Page 1488: ...or idle character is to be transmitted instead of the contents in DATA T9 T0 T9 is used to indicate a break character when 0 and a idle character when 1 the contents of DATA T8 T0 should be zero 0b T...

Page 1489: ...T4 R4T4 Read receive data buffer 4 or write transmit data buffer 4 3 R3T3 R3T3 Read receive data buffer 3 or write transmit data buffer 3 2 R2T2 R2T2 Read receive data buffer 2 or write transmit data...

Page 1490: ...arded Software should only write a MAx field when the associated BAUD MAEN bit is clear 15 10 Reserved 9 0 MA1 Match Address 1 The MA1 and MA2 fields are compared to input data addresses when the most...

Page 1491: ...Common pulse widths are 3 16 1 16 1 32 or 1 4 of the bit length These can be configured by selecting the appropriate oversample ratio and pulse width 00b 1 OSR 01b 2 OSR 10b 3 OSR 11b 4 OSR 15 10 Rese...

Page 1492: ...ot affect the polarity of the receiver RTS RTS will remain negated in the active low state unless TXRTSE is set This bit should only be changed when the transmitter is disabled 0b Transmitter RTS is a...

Page 1493: ...MPT 0 TXOF RXU F W W1C W1C Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 RXIDEN TXOF E RXUF E TXF E TXFIFOSIZ E RXF E RXFIFOSIZ E W TXFLUS H RXFLUS H Reset 0...

Page 1494: ...All data in the transmit FIFO Buffer is cleared out 14 RXFLUSH Receive FIFO Buffer Flush Writing to this field causes all data that is stored in the receive FIFO buffer to be flushed This does not af...

Page 1495: ...Buffer depth 128 datawords 111b Transmit FIFO Buffer depth 256 datawords 3 RXFE Receive FIFO Enable When this field is set the built in FIFO structure for the receive buffer is enabled The size of th...

Page 1496: ...number of datawords that are in the receive FIFO buffer If a dataword is being received that is in the receive shift register it is not included in the count This value may be used in conjunction wit...

Page 1497: ...ate generator The following describes each of the blocks of the LPUART 47 4 1 Clocking and Resets Table 47 2 Clocks LPUART Functional clock The LPUART functional clock is asynchronous to the bus clock...

Page 1498: ...e the exact target frequency Synchronization with the asynchronous LPUART baud clock can cause phase shift The baud rate generation is a free running counter that continues whenever the transmitter or...

Page 1499: ...aracters originally used to gain the attention of old teletype receivers Break characters are a full character time of logic 0 9 bit to 12 bit times including the start and stop bits A longer break of...

Page 1500: ...0 X 1 X 0 12 bit times 0 X 1 X 1 13 bit times 1 0 0 0 0 13 bit times 1 0 0 0 1 13 bit times 1 0 0 1 0 12 bit times 1 0 0 1 1 12 bit times 1 1 0 X 0 14 bit times 1 1 0 X 1 14 bit times 1 X 1 X 0 15 bi...

Page 1501: ...is unaffected by its CTS_B signal RTS_B will remain asserted until the transfer is completed even if the transmitter is disabled mid way through a data transfer 47 4 3 4 Transceiver driver enable usin...

Page 1502: ...ll character time after RDRF is set before the data in the receive data buffer must be read to avoid a receiver overrun When a program detects that the receive data register is full STAT RDRF 1 it get...

Page 1503: ...any extra falling edges anywhere in the character frame 47 4 4 2 Receiver wakeup operation Receiver wakeup and receiver address matching is a hardware mechanism that allows an LPUART receiver to igno...

Page 1504: ...d for idle line wakeup In this mode CTRL RWU is cleared automatically when the receiver detects a full character time of the idle line level The CTRL M CTRL M7 and BAUD M10 control bit selects 7 bit t...

Page 1505: ...ls 11 the receiver is configured for data match wakeup In this mode CTRL RWU is cleared automatically when the receiver detects a character that matches MATCH MA1 field when BAUD MAEN1 is set or that...

Page 1506: ...s then no transfer is made to the receive data buffer and all following frames until the next idle condition are also discarded If both the BAUD MAEN1 and BAUD MAEN2 bits are negated the receiver oper...

Page 1507: ...use the receiver data register to be full The receiver asserts RTS_B when the number of characters in the receiver data register is not full and has not detected a start bit that will cause the receiv...

Page 1508: ...it detection The value sent to the receiver is changed from 1 to a 0 Then if a noise pulse occurs outside the receiver s bit time sampling period then the delay of a 0 is not recorded as noise 47 4 5...

Page 1509: ...ous start bit any data bits and stop bits count towards the idle character detection or from the previous stop bit The number of idle characters that must be received before an idle line condition is...

Page 1510: ...r specification defines a half duplex infrared communication link for exchanging data The full standard includes data rates up to 16 Mbits s This module covers data rates only between 2 4 kbits s and...

Page 1511: ...nsmit character to the DATA register If the transmit interrupt enable CTRL TIE bit is set a hardware interrupt is requested when STAT TDRE is set Transmit complete STAT TC indicates that the transmitt...

Page 1512: ...T RXEDGIF flag to set The STAT RXEDGIF flag is cleared by writing a 1 to it This function depends on the receiver being enabled CTRL RE 1 47 4 8 Peripheral Triggers The connection of the LPUART periph...

Page 1513: ...logically ANDed with the TXD output The input trigger is expected to be generated from a PWM source with a period that is less than the bit clock frequency The input trigger can be connected in place...

Page 1514: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 1514 NXP Semiconductors...

Page 1515: ...modes NOTE Accessing FlexIO registers with FlexIO peripheral clock FlexIO clock disabled will result in transfer error or stall the bus 48 2 Introduction 48 2 1 Overview The FlexIO is a highly configu...

Page 1516: ...Shifter concatenation to support large transfer sizes Automatic start stop bit generation Interrupt DMA or polled transmit receive operation Programmable baud rates independent of bus clock frequency...

Page 1517: ...modes described in the following table Table 48 2 Chip modes supported by the FlexIO module Chip mode FlexIO Operation Run Normal operation Debug Can continue operating provided the Debug Enable bit...

Page 1518: ...nable SHIFTEIEN 32 RW 0000_0000h 28h Timer Interrupt Enable Register TIMIEN 32 RW 0000_0000h 30h Shifter Status DMA Enable SHIFTSDEN 32 RW 0000_0000h 80h 8Ch Shifter Control N Register SHIFTCTL0 SHIFT...

Page 1519: ...ersion Number This read only field returns the major version number for the module specification 23 16 MINOR Minor Version Number This read only field returns the minor version number for the module s...

Page 1520: ...0 0 0 0 1 0 0 48 3 1 3 3 Fields Field Function 31 24 TRIGGER Trigger Number Number of external triggers implemented 23 16 PIN Pin Number Number of Pins implemented 15 8 TIMER Timer Number Number of T...

Page 1521: ...requires the FlexIO functional clock to be at least twice the frequency of the bus clock 0b Configures for normal register accesses to FlexIO 1b Configures for fast register accesses to FlexIO 1 SWRS...

Page 1522: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PDI W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 3 1 5 3 Fields Field Function 31 8 Reserved 7 0 PDI Pin Data Input Returns the input data on each of the FlexIO...

Page 1523: ...FTBUF data has been transferred to the Shifter SHIFTBUF is empty or when initially configured for SMOD Transmit and the status flag is cleared when the SHIFTBUF register is written For SMOD Match Stor...

Page 1524: ...h the expected value For SMOD Transmit indicates Shifter was ready to load new data from SHIFTBUF before new data had been written into SHIFTBUF SHIFTBUF Underrun For SMOD Match Store indicates a matc...

Page 1525: ...flag In 8 bit baud counter mode the timer status flag is set when the upper 8 bit counter equals zero and decrements In 8 bit high PWM mode the timer status flag is set when the upper 8 bit counter eq...

Page 1526: ...3 Fields Field Function 31 4 Reserved 3 0 SSIE Shifter Status Interrupt Enable Enables interrupt generation when corresponding SSF is set 0b Shifter Status Flag interrupt disabled 1b Shifter Status Fl...

Page 1527: ...0 3 Fields Field Function 31 4 Reserved 3 0 SEIE Shifter Error Interrupt Enable Enables interrupt generation when corresponding SEF is set 0b Shifter Error Flag interrupt disabled 1b Shifter Error Fla...

Page 1528: ...11 3 Fields Field Function 31 4 Reserved 3 0 TEIE Timer Status Interrupt Enable Enables interrupt generation when corresponding TSF is set 0b Timer Status Flag interrupt is disabled 1b Timer Status Fl...

Page 1529: ...Reserved 3 0 SSDE Shifter Status DMA Enable Enables DMA request generation when corresponding SSF is set 0b Shifter Status Flag DMA request is disabled 1b Shifter Status Flag DMA request is enabled 48...

Page 1530: ...ins configured as an output PINCFG 11 this field will take effect when the register is written 00b Shifter pin output disabled 01b Shifter pin open drain or bidirectional output enable 10b Shifter pin...

Page 1531: ...inuous mode Shifter data is continuously compared to SHIFTBUF contents 110b Reserved 111b Reserved 48 3 1 14 Shifter Configuration N Register SHIFTCFG0 SHIFTCFG3 48 3 1 14 1 Offset Register Offset SHI...

Page 1532: ...Transmitter outputs stop bit value 1 on store receiver match store sets error flag if stop bit is not 1 3 2 Reserved 1 0 SSTART Shifter Start bit For SMOD Transmit this field allows automatic start bi...

Page 1533: ...ding shifter status flag is set indicating new Shifter data is available For SMOD Transmit SHIFTBUF data is transferred into the Shifter before the Timer begins For SMOD Match Store SHIFTBUF 31 16 con...

Page 1534: ...t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SHIFTBUFBIS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 3 1 16 3 Fields Field Function 31 0 SHIFTBUFBIS Shift Buffer Alias...

Page 1535: ...0 0 0 0 0 0 48 3 1 17 3 Fields Field Function 31 0 SHIFTBUFBYS Shift Buffer Alias to SHIFTBUF register except reads writes to this register are byte swapped Reads return SHIFTBUF 7 0 SHIFTBUF 15 8 SH...

Page 1536: ...eld Function 31 0 SHIFTBUFBBS Shift Buffer Alias to SHIFTBUF register except reads writes to this register are bit swapped within each byte Reads return SHIFTBUF 24 31 SHIFTBUF 16 23 SHIFTBUF 8 15 SHI...

Page 1537: ...external trigger selection NOTE For a pin N 0 to 7 For a Shifter N 0 to 3 For a Timer N 0 to 3 When TRGSRC 0 the trigger selection is configured as follows N External trigger N input When TRGSRC 1 the...

Page 1538: ...gister is written 0b Pin is active high 1b Pin is active low 6 2 Reserved 1 0 TIMOD Timer Mode In 8 bit baud counter mode the lower 8 bits of the counter and compare register are used to configure the...

Page 1539: ...r is actually at logic level 1 if the TRGPOL is set to 1 active low 48 3 1 20 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 TIMOUT 0 TIMDEC 0 TIMRST W Reset 0 0 0 0 0 0 0 0 0 0 0...

Page 1540: ...Output 011b Timer reset on Timer Trigger equal to Timer Output 100b Timer reset on Timer Pin rising edge 101b Reserved 110b Timer reset on Trigger rising edge 111b Timer reset on Trigger rising or fal...

Page 1541: ...1b Stop bit is enabled on timer compare 10b Stop bit is enabled on timer disable 11b Stop bit is enabled on timer compare and timer disable 3 2 Reserved 1 TSTART Timer Start Bit When start bit is enab...

Page 1542: ...put to CMP 7 0 1 and the upper 8 bits configure the low period of the output to CMP 15 8 1 In 16 bit counter mode the compare value can be used to generate the baud rate divider if shift clock source...

Page 1543: ...r out of the FlexIO The timing of shift load and store events are controlled by the Timer assigned to the Shifter via the SHIFTCTL TIMSEL register The Shifters are designed to support either DMA inter...

Page 1544: ...2 2 Receive Mode When configured for Receive mode SHIFTCTL SMOD Receive the shifter will shift data in and store data into the SHIFTBUF register when a store event is signalled by the assigned Timer...

Page 1545: ...o 16 bits of data can be compared using SHIFTBUF 31 16 to configure the data to be matched and SHIFTBUF 15 0 to mask the match result The Shifter Status Flag SHIFTSTAT SSF and any enabled interrupts o...

Page 1546: ...pper 8 bits decrement when the lower 8 bits equal zero and decrement Note that a timer reset event in 8 bit Baud Counter Mode will only reset the lower 8 bit counter the upper 8 bit counter is not aff...

Page 1547: ...mer do not see this as a rising edge on the timer shift clock Transmit shifters controlled by this timer will either output their start bit value or load the shift register from the shift buffer and o...

Page 1548: ...his timer will output their stop bit value if configured by SSTOP Receive shifters controlled by this timer will store the contents of the shift register in their shift buffer as configured by SSTOP O...

Page 1549: ...be output on the pin or to control the enable on the bidirectional output Any timer or shifter could be configured to control the output enable for a pin where the bidirectional output data is driven...

Page 1550: ...Shifter Status Flag Y Y Y SEF Shifter Error Flag Y N Y TSF Timer Status Flag Y N Y 48 4 6 Peripheral Triggers The connection of the FlexIO peripheral triggers with other peripherals are device specifi...

Page 1551: ...register remains unaltered allowing an address mark bit or additional stop bit to remain undisturbed FlexIO does not support automatic insertion of parity bits Table 48 4 UART Transmit Configuration...

Page 1552: ...n the incoming data another Timer can also be used to detect an idle line of programmable length Break characters will cause the error flag to set and the shifter buffer register will return 0x00 Flex...

Page 1553: ...n 0x0000_0F01 Configure 8 bit transfer with baud rate of divide by 4 of the FlexIO clock Set TIMCMP 15 8 number of bits x 2 1 Set TIMCMP 7 0 baud rate divider 2 1 TIMCFGn 0x0204_2522 Configure start b...

Page 1554: ...1 0x0000_0000 Start and stop bit disabled SHIFTCTL n 1 0x0000_0101 Configure receive using Timer 0 on posedge of clock with input data on Pin 1 TIMCMPn 0x0000_3F01 Configure 32 bit transfer with baud...

Page 1555: ...TIMCMP 15 8 number of bits x 2 1 Set TIMCMP 7 0 baud rate divider 2 1 TIMCFGn 0x0100_2222 Configure start bit stop bit enable on trigger high and disable on compare initial clock state is logic 0 TIM...

Page 1556: ...cycles so the maximum baud rate is divide by 6 of the FlexIO clock frequency Table 48 9 SPI Slave CPHA 0 Configuration Register Value Comments SHIFTCFGn 0x0000_0000 Start and stop bit disabled SHIFTCT...

Page 1557: ...clock with input data on Pin 1 TIMCMPn 0x0000_003F Configure 32 bit transfer Set TIMCMP 15 0 number of bits x 2 1 TIMCFGn 0x0120_6602 Configure start bit enable on trigger rising edge disable on trig...

Page 1558: ...ng and the receive shifter returns the data actually present on the SDA pin The transmit shifter will load 1 additional word on the last falling edge of SCL pin this word should be 0x00 if generating...

Page 1559: ...open drain with Shifter 0 flag as the inverted trigger TIMCMP n 1 0x0000_000F Configure 8 bit transfer Set TIMCMP 15 0 number of bits x 2 1 TIMCFG n 1 0x0020_1112 Enable when Timer 0 is enabled disab...

Page 1560: ...on falling edge of clock with input data on Pin 1 TIMCMPn 0x0000_3F01 Configure 32 bit transfer with baud rate of divide by 4 of the FlexIO clock Set TIMCMP 15 8 number of bits x 2 1 Set TIMCMP 7 0 ba...

Page 1561: ...s a maximum 1 5 cycle delay on the clock synchronization plus 1 cycle to output the data Timer 2 detects the falling edge of frame sync start of new frame and asserts output until falling edge of bit...

Page 1562: ...e trigger TIMCMP n 2 0x0000_0000 Compare on zero first edge TIMCFG n 2 0x0020_6400 Configure enable on inverted pin frame sync rising edge and disable on trigger falling edge bit clock initial clock s...

Page 1563: ...s Yes 0x00A0_0000 FlexCAN1 32 MBs Yes No No 0x00A0_0000 FlexCAN2 16 MBs No No No 0x00B0_0000 WCT1016S FlexCAN0 32 MBs Yes Yes Yes 0x00A0_0000 FlexCAN1 32 MBs Yes No No 0x00A0_0000 FlexCAN2 32 MBs Yes...

Page 1564: ...se of CAN FD frames Form error or Form error in Data Phase of CAN FD frames Stuffing error or Stuffing error in Data Phase of CAN FD frames Transmit error warning Receive error warning CAN FD error Bi...

Page 1565: ...e mode entry to place the FlexCAN module in that mode On this chip the FlexCAN module cannot directly enter Module Disable mode Stop mode To enter these modes the FlexCAN module must first enter Freez...

Page 1566: ...1 8 2 Module Disable mode entry See Module Disable mode for details about this mode CAUTION In the detailed description of this mode the list of FlexCAN behavior that begins with If the module is disa...

Page 1567: ...ich describes the main subblocks implemented in the FlexCAN module including One associated memory for storing message buffers Receive Global Mask registers Receive Individual Mask registers Receive F...

Page 1568: ...n the CAN bus Requesting RAM access for receiving and transmitting message frames Validating received messages Performing error handling Detecting CAN FD messages The Controller Host Interface CHI sub...

Page 1569: ...n 16 bit free running timer with an optional external time tick Global network time synchronized by a specific message Maskable interrupts Independence from the transmission medium an external transce...

Page 1570: ...performs an internal loop back that can be used for self test operation The bit stream output of the transmitter is internally fed back to the receiver input The Rx CAN input pin is ignored and the Tx...

Page 1571: ...de is done by negating MCR MDIS See Module Disable mode for more information Stop mode This low power mode is entered when Stop mode is requested at chip level and MCR LPM_ACK is asserted by the FlexC...

Page 1572: ...Tx This pin is the transmit pin to the CAN bus transceiver Dominant state is represented by logic level 0 Recessive state is represented by logic level 1 49 4 Memory map register definition This sect...

Page 1573: ...s Interrupt Masks 1 register IMASK1 S U Yes Yes Interrupt Flags 1 register IFLAG1 S U Yes Yes Control 2 Register CTRL2 S U Yes No Error and Status 2 Register ESR2 S U Yes Yes CRC Register CRCR S U Yes...

Page 1574: ...store CAN messages for transmission and reception using mailboxes and Rx FIFO structures 49 4 2 CAN register descriptions The table below shows the FlexCAN memory map The address range from offset 0x...

Page 1575: ...h Pretended Networking ID Filter 2 Register ID Mask register FLT_ ID2_IDMASK 32 RW 0000_0000h B20h Pretended Networking Payload Low Filter 2 Register Payload Low Mask register PL2_PLMASK_LO 32 RW 0000...

Page 1576: ...Offset MCR 0h 49 4 2 2 2 Function This register defines global system configurations such as the module operation modes and the maximum message buffer configuration 49 4 2 2 3 Diagram Bits 31 30 29 28...

Page 1577: ...ear it after initializing the message buffers and the Control registers CTRL1 and CTRL2 No reception or transmission is performed by FlexCAN before this bit is cleared Freeze mode cannot be entered wh...

Page 1578: ...ables the generation of the TWRNINT and RWRNINT flags in the Error and Status Register 1 ESR1 If WRNEN is negated the TWRNINT and RWRNINT flags will always be zero independent of the values of the err...

Page 1579: ...under Pretended Networking mode This bit can be written in Freeze mode only NOTE This field is not supported in every instance The following table includes only supported registers Field supported in...

Page 1580: ...tandard IDs or two partial 14 bit standard and extended IDs per ID filter table element 10b Format C Four partial 8 bit standard IDs per ID filter table element 11b Format D All frames rejected 7 Rese...

Page 1581: ...use the PRESDIV RJW PSEG1 PSEG2 and PROPSEG fields of the CTRL1 register for CAN bit timing Instead use the CBT register s EPRESDIV ERJW EPSEG1 EPSEG2 and EPROPSEG fields The contents of this register...

Page 1582: ...vides a mask for the Error interrupt ESR1 ERRINT 0b Error interrupt disabled 1b Error interrupt enabled 13 CLKSRC CAN Engine Clock Source This bit selects the clock source to the CAN Protocol Engine P...

Page 1583: ...s bit defines how FlexCAN recovers from Bus Off state If this bit is negated automatic recovering from Bus Off state occurs according to the CAN Specification 2 0B If the bit is asserted automatic rec...

Page 1584: ...1 FLTCONF indicating Passive Error There can be some delay between the Listen Only mode request and acknowledge This bit can be written in Freeze mode only because it is blocked by hardware in other m...

Page 1585: ...message If CTRL1 TSYN is asserted the timer is reset whenever a message is received in the first available mailbox according to CTRL2 RFFN setting The CPU can write to this register anytime However if...

Page 1586: ...mailbox filter bits RXMGMASK is used to mask the filter fields of all Rx MBs excluding MBs 14 15 which have individual mask registers This register can only be written in Freeze mode as it is blocked...

Page 1587: ...the incoming frame 3 If CTRL2 EACEN is negated the IDE bit of mailbox is always compared with the IDE bit of the incoming frame 0b The corresponding bit in the filter is don t care 1b The correspondi...

Page 1588: ...bit masks the corresponding mailbox 14 filter field in the same way that RXMGMASK masks other mailboxes filters See the description of the RXMGMASK register 0b The corresponding bit in the filter is...

Page 1589: ...Function 31 0 RX15M Rx Buffer 15 Mask Bits Each mask bit masks the corresponding mailbox 15 filter field in the same way that RXMGMASK masks other mailboxes filters See the description of the RXMGMAS...

Page 1590: ...r equal to 127 when the other already satisfies this condition ESR1 FLTCONF is updated to reflect Error Active state If the value of TXERRCNT becomes greater than 255 ESR1 FLTCONF is updated to reflec...

Page 1591: ...working mode RXERRCNT and RXERRCNT_FAST keep counting errors and error flags are stored TXERRCNT and TXERRCNT_FAST preserve their values and do not change because no transmission occurs under Pretende...

Page 1592: ...ode where it can be written by the CPU 7 0 TXERRCNT Transmit Error Counter Transmit error counter for all errors detected in transmitted messages The TXERRCNT counter is read only except in Freeze mod...

Page 1593: ...its This action clears the respective bits that were set since the last read access 2 Write 1 to clear the interrupt bit that has triggered the interrupt request 3 Write 1 to clear the ERR_OVR bit if...

Page 1594: ...ase of CAN FD frames with the BRS bit set 0b No such occurrence 1b At least one bit sent as recessive is received as dominant 30 BIT0ERR_FAST Bit0 Error in the Data Phase of CAN FD frames with the BRS...

Page 1595: ...set when the Tx Error Counter TXERRCNT has finished counting 128 occurrences of 11 consecutive recessive bits on the CAN bus and is ready to leave Bus Off If the corresponding mask bit in the Control...

Page 1596: ...between the transmitted and the received bit in a non CAN FD message or in the arbitration or data phase of a CAN FD message This bit is updated when FlexCAN returns to Normal mode from Pretended Net...

Page 1597: ...dicates if FlexCAN is transmitting a message See the table in the overall ESR1 register description 0b FlexCAN is not transmitting a message 1b FlexCAN is transmitting a message 5 4 FLTCONF Fault Conf...

Page 1598: ...set Register Offset IMASK1 28h 49 4 2 10 2 Function This register allows any number of a range of the 32 message buffer interrupts to be enabled or disabled for MB31 to MB0 It contains one interrupt m...

Page 1599: ...1 to it Writing 0 has no effect There is an exception when DMA for Rx FIFO is enabled as described below The BUF7I to BUF5I flags are also used to represent FIFO interrupts when the Rx FIFO is enabled...

Page 1600: ...is greater than the MCR MAXMB to be updated otherwise they will remain set and be inconsistent with the number of MBs available 49 4 2 11 3 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1...

Page 1601: ...writes When MCR RFEN is set Rx FIFO enabled the BUF5I flag represents Frames available in Rx FIFO and indicates that at least one frame is available to be read from the Rx FIFO When the MCR DMA bit is...

Page 1602: ...by Rx FIFO and ID filter table Remaining available mailboxes Rx FIFO ID filter table elements affected by Rx individual masks Rx FIFO ID filter table elements affected by Rx FIFO global mask 0x0 8 MB...

Page 1603: ...errupt in ESR1 register 0b Bus off done interrupt disabled 1b Bus off done interrupt enabled 29 Reserved 28 Reserved 27 24 RFFN Number Of Rx FIFO Filters This 4 bit field defines the number of Rx FIFO...

Page 1604: ...b Matching starts from mailboxes and continues on Rx FIFO 17 RRS Remote Request Storing If this bit is asserted a remote request frame is submitted to a matching process and stored in the correspondin...

Page 1605: ...ld is writable only in Freeze mode NOTE FlexCAN is able to transmit FD frame format according to CAN Protocol standard ISO 11898 1 0b FlexCAN operates using the non ISO CAN FD protocol 1b FlexCAN oper...

Page 1606: ...nactive mailbox see the ESR2 IMB bit description If there is no inactive mailbox then the mailbox indicated depends on the value of CTRL1 LBUF If CTRL1 LBUF is negated then the mailbox indicated is th...

Page 1607: ...er 0b1000 or 0b0000 This bit is asserted in the following cases During arbitration if an ESR2 LPTM is found and it is inactive If ESR2 IMB is not asserted and a frame is transmitted successfully This...

Page 1608: ...d Function 31 23 Reserved 22 16 MBCRC CRC Mailbox This field indicates the number of the mailbox corresponding to the value in CRCR TXCRC field 15 Reserved 14 0 TXCRC Transmitted CRC value This field...

Page 1609: ...DB 1 RXIDC 2 Reserved A FGM 31 FGM 30 FGM 29 1 FGM 0 B FGM 31 FGM 15 FGM 30 FGM 14 FGM 29 16 FGM 13 0 C FGM 31 24 FGM 23 16 FGM 15 8 FGM 7 0 1 If MCR IDAM is equivalent to format B only the fourteen m...

Page 1610: ...ugh which the CPU accesses the output of the RXFIR FIFO located in RAM The RXFIR FIFO is written by the FlexCAN whenever a new message is moved into the Rx FIFO Also its output is updated whenever the...

Page 1611: ...er is an alternative way to store the CAN bit timing variables described in CTRL1 register EPRESDIV EPROPSEG EPSEG1 EPSEG2 and ERJW are extended versions of PRESDIV PROPSEG PSEG1 PSEG2 and RJW fields...

Page 1612: ...es Sclock frequency PE clock frequency EPRESDIV 1 20 16 ERJW Extended Resync Jump Width This 5 bit field defines the maximum number of time quanta that a bit time can be changed by one re synchronizat...

Page 1613: ...is negated an individual mask is provided for each available Rx mailbox on a one to one correspondence When the Rx FIFO is enabled MCR RFEN bit is asserted an individual mask is provided for each Rx...

Page 1614: ...on For Rx FIFO ID filter table elements see the RXFGMASK register description 0b The corresponding bit in the filter is don t care 1b The corresponding bit in the filter is checked 49 4 2 19 Pretended...

Page 1615: ...S FC S W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 49 4 2 19 4 Fields Field Function 31 18 Reserved 17 WTOF_MSK Wake Up by Timeout Flag Mask Bit This bit masks the generation of a wakeup event originated...

Page 1616: ...ch upon a payload value inside a range greater than or equal to a specified lower limit and smaller than or equal to a specified upper limit 3 2 IDFS ID Filtering Selection This 2 bit field selects th...

Page 1617: ...0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R MATCHTO W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 49 4 2 20 4 Fields Field Function 31 16 Reserved 15 0 MATCHTO Timeout for No Message...

Page 1618: ...h register WU_MTC 49 4 2 21 1 Offset Register Offset WU_MTC B08h 49 4 2 21 2 Function This read only register contains wakeup information related to the matching processes performed while FlexCAN rece...

Page 1619: ...Wake Up by Match Flag Bit This bit identifies whether the FlexCAN has detected a matching Rx incoming message which passed the filtering criteria specified in CTRL1_PN register This flag generates a...

Page 1620: ...n in Freeze mode only NOTE Each module instance supports a different number of registers Register supported Register not supported FlexCA N0_FLT _ID1 FlexCA N1_FLT _ID1 FlexCA N2_FLT _ID1 49 4 2 22 3...

Page 1621: ...xtended frame format considering all bits or the 11 bits of a standard frame format considering just the 11 leftmost bits 49 4 2 23 Pretended Networking DLC Filter register FLT_DLC 49 4 2 23 1 Offset...

Page 1622: ...0 0 0 49 4 2 23 4 Fields Field Function 31 20 Reserved 19 16 FLT_DLC_LO Lower Limit for Length of Data Bytes Filter This field specifies the lower limit for the number of data bytes considered valid...

Page 1623: ...payload It is used either for equal to smaller than or equal greater than or equal comparisons or as the lower limit value in a payload range detection It can be written in Freeze mode only NOTE Each...

Page 1624: ...r 1 low order bits for Pretended Networking payload filtering corresponding to data byte 2 7 0 Data_byte_3 Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to d...

Page 1625: ...9 4 2 25 4 Fields Field Function 31 24 Data_byte_4 Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 4 23 16 Data_byte_5 Payload Filter 1 high orde...

Page 1626: ...s used to store the ID mask IDE_MSK and RTR_MSK bits are used in both ID filtering exact and range to enable FLT_IDE and FLT_RTR respectively to be used as part of ID reception filter This register ca...

Page 1627: ...n t care 1b The corresponding bit in the filter is checked 28 0 FLT_ID2_IDMA SK ID Filter 2 for Pretended Networking Filtering ID Mask Bits for Pretended Networking ID Filtering This register is used...

Page 1628: ...be written in Freeze mode only NOTE Each module instance supports a different number of registers Register supported Register not supported FlexCA N0_PL2 _PLMA SK_LO FlexCA N1_PL2 _PLMA SK_LO FlexCA N...

Page 1629: ...orresponding to the data byte 3 49 4 2 28 Pretended Networking Payload High Filter 2 low order bits Payload High Mask register PL2_PLMASK_HI 49 4 2 28 1 Offset Register Offset PL2_PLMASK_HI B24h 49 4...

Page 1630: ...iltering corresponding to the data byte 4 23 16 Data_byte_5 Payload Filter 2 high order bits Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 5 15...

Page 1631: ...ds of an incoming Rx message NOTE The C S registers are located at 0xB40 for WMB0 0xB50 for WMB1 0xB60 for WMB2 and 0xB70 for WMB3 NOTE Each module instance supports a different number of registers Re...

Page 1632: ...standard 1b Frame format is extended 20 RTR Remote Transmission Request Bit This bit identifies whether the frame is remote or not 0b Frame is data one not remote 1b Frame is a remote one 19 16 DLC L...

Page 1633: ...x message NOTE The ID registers are located at 0xB44 for WMB0 0xB54 for WMB1 0xB64 for WMB2 and 0xB74 for WMB3 NOTE Each module instance supports a different number of registers Register supported Reg...

Page 1634: ...g mode This register stores either the 29 bits of the extended frame format considering the ID 28 0 field or the 11 bits of the standard frame format considering the ID 28 18 field only the remaining...

Page 1635: ...and 0xB78 for WMB3 NOTE Each module instance supports a different number of registers Register supported Register not supported FlexCA N0_WM B0_ D03 WMB3_ D03 FlexCA N1_WM B0_ D03 WMB3_ D03 FlexCA N2...

Page 1636: ...32 Wake Up Message Buffer Register Data 4 7 WMB0_D47 WMB3_D47 49 4 2 32 1 Offset Register Offset WMB0_D47 B4Ch WMB1_D47 B5Ch WMB2_D47 B6Ch WMB3_D47 B7Ch 49 4 2 32 2 Function Each of the four WMBs con...

Page 1637: ...5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Data_byte_6 Data_byte_7 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 49 4 2 32 4 Fields Field Function 31 24 Data_byte_4 Received payload corresponding to the data by...

Page 1638: ...an 8 byte payload is selected Block R0 allocates MB0 to MB31 Block R1 allocates MB32 to MB63 When a payload larger than 8 bytes is selected the maximum number of MBs in a block is limited as described...

Page 1639: ...bit during the data phase of Tx messages The CPU can write this bit any time However its effect turns active only when the CAN bus is in Wait for Bus Idle Bus Idle or Bus Off state or when the current...

Page 1640: ...ion The CPU needs to write one to clear it 0b Measured loop delay is in range 1b Measured loop delay is out of range 13 Reserved 12 8 TDCOFF Transceiver Delay Compensation Offset This bit field contai...

Page 1641: ...The contents of this register are not affected by soft reset NOTE The sum of the Fast Propagation Segment FPROPSEG and Fast Phase Segment 1 FPSEG1 must be at least two time quanta NOTE The user must...

Page 1642: ...FD message with the BRS bit set One time quantum is equal to the Sclock period This field can be written only in Freeze mode because it is blocked by hardware in other modes Resync Jump Width FSJW 1...

Page 1643: ...rame formats as shown below The CRC_15 polynomial is used for all frames in CAN format The CRC_17 polynomial is used for frames in CAN FD format with a DATA FIELD up to sixteen bytes The CRC_21 polyno...

Page 1644: ...ransmitted CRC value This 21 bit field contains the CRC value calculated over the most recent transmitted message Different CRC polynomials are used for different frame formats A 15 bit polynomial CRC...

Page 1645: ...Data byte 10 Data byte 11 0x14 Data byte 12 Data byte 13 Data byte 14 Data byte 15 0x18 Data byte 16 Data byte 17 Data byte 18 Data byte 19 0x1C Data byte 20 Data byte 21 Data byte 22 Data byte 23 0x2...

Page 1646: ...icipate in the matching process 0b0100 EMPTY MB is active and empty EMPTY FULL When a frame is received successfully after the Move in process the CODE field is automatically updated to FULL 0b0010 FU...

Page 1647: ...OVERRUN See Matching process for details about overrun behavior 0b1010 RANSWER4 A frame was configured to recognize a Remote Request frame and transmit a Response frame in return 5 RANSWER TANSWER 0b1...

Page 1648: ...the corresponding MB does not participate in the matching process Table 49 11 Message buffer code for Tx buffers CODE Description Tx Code BEFORE tx frame MB RTR Tx Code AFTER successful transmission...

Page 1649: ...n arbitration loss 1 Recessive value is compulsory for transmission in extended format frames 0 Dominant is not a valid value for transmission in extended format frames IDE ID Extended Bit This field...

Page 1650: ...e Stamp This 16 bit field is a copy of the Free Running Timer captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus PRIO Local priority This 3 bit...

Page 1651: ...xCAN RAM can be partitioned in blocks of 512 bytes Each block can accommodate a number of message buffers which depends on the configuration provided by FDCTRL MBDSRn bit fields as shown in table belo...

Page 1652: ...f MBs in the RAM block Message buffer range 0 FDCTRL MBDSR0 00 8 bytes payload 32 0 to 31 49 4 5 FlexCAN message buffer memory map The FlexCAN memory buffers are allocated in memory according to the t...

Page 1653: ...260 MB30 0270 MB31 Table 49 16 16 byte message buffers Address offset hex MBDSR b01 16 byte payload 0080 MB0 0098 MB1 00B0 MB2 00C8 MB3 00E0 MB4 00F8 MB5 0110 MB6 0128 MB7 0140 MB8 0158 MB9 0170 MB10...

Page 1654: ...MB5 0230 MB6 49 4 6 Rx FIFO structure When MCR RFEN is set the memory area from 0x80 to 0xDC which is normally occupied by MBs 0 5 is used by the reception FIFO engine The region 0x80 0x8C contains th...

Page 1655: ...e 4 Data byte 5 Data byte 6 Data byte 7 0x90 to 0xDC Reserved 0xE0 ID filter table element 0 0xE4 ID filter table element 1 0xE8 to 0x2D4 ID filter table elements 2 to 125 0x2D8 ID filter table elemen...

Page 1656: ...t significant bits 29 to 19 are used for frame identification In the extended frame format all bits are used RXIDB_0 RXIDB_1 Rx frame identifier Format B Specifies an ID to be used as acceptance crite...

Page 1657: ...ithm decides the prioritization of MBs to be transmitted based on the message ID optionally augmented by 3 local priority bits or the MB ordering Before proceeding with the functional description an i...

Page 1658: ...on to maximize software performance If the fields are configured in separate writes the MB_CS CODE must be the last write in the C S word When the MB is activated it participates in the arbitration pr...

Page 1659: ...owest number mailbox and runs toward the higher ones The arbitration process is triggered in the following events From the CRC field of the CAN frame The start point depends on the value of CTRL2 TASD...

Page 1660: ...values the mailbox with the lowest number is the arbitration winner The composition of the arbitration value depends on the MCR LPRIOEN setting 49 5 2 2 1 Local priority disabled If MCR LPRIOEN is ne...

Page 1661: ...nd the corresponding IFLAG bit is cleared by the CPU FlexCAN enters Freeze mode or Bus Off FlexCAN loses the bus arbitration or there is an error during the transmission At the first opportunity windo...

Page 1662: ...e mode request in Idle state Arbitration is considered pending as described below It was not possible to finish arbitration process in time C S write during arbitration if write is performed in a MB w...

Page 1663: ...g procedure 1 Read the Control and Status word of that mailbox 2 Check if the BUSY bit is deasserted indicating that the mailbox is locked Repeat step 1 while it is asserted See Mailbox lock mechanism...

Page 1664: ...upt by writing one to IFLAG1 BUF5I mandatory releases the MB and allows the CPU to read the next Rx FIFO entry When MCR DMA is asserted upon receiving a frame in FIFO IFLAG1 BUF5I generates a DMA requ...

Page 1665: ...th the matching elements of the Rx SMB that is receiving the frame on the CAN bus The Rx SMB has the same structure as a mailbox The reception structures Rx FIFO or mailboxes associated with the match...

Page 1666: ...o receive matched mailbox 2 the last non free to receive matched mailbox It is possible to select the priority of scan between mailboxes and Rx FIFO with CTRL2 MRP If the selected priority is Rx FIFO...

Page 1667: ...me lost by no match 1 1 X Free None First Mb 1 1 X Not free None Last MB Overrun FIFO enabled Queue disabled 1 0 0 X Not full6 FIFO 1 0 0 None Full7 None Frame lost by FIFO full FIFO overflow 1 0 0 Fr...

Page 1668: ...arrives the matching algorithm finds MB number 2 again but it is not free to receive so it keeps looking finds MB number 5 and stores the message there If yet another message with the same ID arrives...

Page 1669: ...AN PN registers PN control registers are described in Pretended Networking Control 1 Register CTRL1_PN and Pretended Networking Control 2 Register CTRL2_PN The control bit fields that configure the fi...

Page 1670: ...sk is not used See CTRL1_PN IDFS in Pretended Networking Control 1 register CTRL1_PN The above criteria for ID filtering must be coherent with FLT_IDE and FLT_RTR target values in FLT_ID1 register Onl...

Page 1671: ...to the FLT_DLC_HI upper limit Conversely a DLC value out of the specified range results in a mismatch By making FLT_DLC_LO FLT_DLC_HI only payloads of the specified quantity of bytes will be filtered...

Page 1672: ...counting until the CPU wakes up Conversely if the timeout counter reaches the target value then the message filtering process continue to filter incoming messages until the CPU wakes up WU_MTC MCOUNT...

Page 1673: ...Clock domains and restrictions FlexCAN continues to receive Rx incoming messages but only compares them to the predefined target values and in accordance with the selected filtering criteria The matc...

Page 1674: ...iving a frame transmitted by the FlexCAN itself and self reception is disabled MCR SRXDIS is asserted Any CAN protocol error is detected Note that the pending move in is not cancelled if the module en...

Page 1675: ...Counter is in the 124 to 128 range During Bus Idle state During Wait For Bus Idle state The move out process is not atomic Only the CPU has priority to access the memory concurrently out of Bus Idle s...

Page 1676: ...refore The abort code is written into the CODE field The interrupt flag is set in the IFLAG An interrupt is optionally generated to the CPU If the CPU writes the abort code before the transmission beg...

Page 1677: ...m NOTE Message buffers that are part of the Rx FIFO cannot be inactivated There is no write protection on the FIFO region by FlexCAN CPU must maintain data coherency in the FIFO region when RFEN is as...

Page 1678: ...e MB the BUSY bit on the CODE field is asserted If the CPU reads the Control and Status word and finds out that the BUSY bit is set it should defer accessing the MB until the BUSY bit is negated Note...

Page 1679: ...message reissuing the interrupt to the CPU Otherwise the flag remains negated The output of the FIFO is valid only while IFLAG1 BUF5I is asserted IFLAG1 BUF6I Rx FIFO Warning is asserted when the numb...

Page 1680: ...le is affected by RXFGMASK NOTE For more information about the difference between FD and non FD regarding this feature see Table 49 3 49 5 8 1 Rx FIFO under DMA operation The receive only FIFO can sup...

Page 1681: ...ASKs are not used to mask the generation of DMA requests NOTE For more information about the difference between FD and non FD regarding this feature see Table 49 3 49 5 8 2 Clear FIFO operation When M...

Page 1682: ...ges interleaved with Classical CAN messages There are three additional control bits in the CAN FD frame The Extended Data Length EDL bit enables a longer data payload with different data length coding...

Page 1683: ...CAN frames with 29 bit identifiers are decoded as an EDL bit not a reserved one A CAN FD frame is recognized by a recessive EDL bit and a Classical CAN frame is recognized by a dominant EDL bit The BR...

Page 1684: ...ase error This situation can occur after the switch from arbitration to data phase and will last until the next synchronization event Thus the length of the time quantum should be the same in nominal...

Page 1685: ...m for CAN FD messages NOTE In Classical CAN frames the CRC delimiter is one single recessive bit In CAN FD frames the CRC delimiter may consist of one or two recessive bits FlexCAN sends only one rece...

Page 1686: ...is used for frames in CAN FD format with a data field longer than sixteen bytes Each polynomial results in a Hamming distance of 6 At the start of the frame all three CRC polynomials are calculated co...

Page 1687: ...and STFERR_FAST to individually indicate the occurrence of errors in the data phase of CAN FD frames with the BRS bit set There is no ACKERR detected in the data phase of a CAN FD frame Fault confine...

Page 1688: ...it set When it is active a comparison is done between the real received bit and the delayed transmitted bit where the delay is calculated based on the measured transceiver loop delay NOTE The actual v...

Page 1689: ...ably the offset has to use optimal settings To be sure the bit sampling is performed in the best region the TDC offset should be configured as shown in this equation Offset FPSEG1 FPROPSEG 2 x FPRESDI...

Page 1690: ...a frame in response The mask registers are not used in remote frame matching and all ID bits except RTR of the incoming received frame should match In the case that a remote request frame is received...

Page 1691: ...e CAN bus and is stored at the end of move in in the TIME STAMP field providing network behavior with respect to time When CTRL2 TIMER_SRC is asserted the free running timer is continuously clocked by...

Page 1692: ...AN module supports a variety of means to set up bit timing parameters that are required by the CAN protocol The Control 1 register CTRL1 has various fields used to control bit timing parameters PRESDI...

Page 1693: ...FDCBT instead so that their sum plus 1 is in the range of 2 to 39 time quanta Time Segment 2 This segment represents the phase segment 2 of the CAN standard It can be programmed by setting CTRL1 PSEG2...

Page 1694: ...mple Point single or triple sampling Tq Tq 8 25 Time Quanta 1 Bit Time 2 8 NRZ Signal Figure 49 7 Segments within the bit time example using CTRL1 bit timing variables for Classical CAN format Functio...

Page 1695: ...segment syntax Syntax Description SYNC_SEG System expects transitions to occur on the bus during this period TSEG1 Corresponds to the sum of PROPSEG and PSEG1 TSEG2 Corresponds to the PSEG2 value Tran...

Page 1696: ...s the Protocol Engine PE Clock see Figure 49 6 in Hz fSYS is the frequency of operation of the system CHI clock in Hz PSEG1 is the value in CTRL1 PSEG1 field PSEG2 is the value in CTRL1 PSEG2 field PR...

Page 1697: ...not take into account the delay caused by the concurrent memory access due to the CPU or other internal FlexCAN subblocks 49 5 9 9 Tx arbitration start delay CTRL2 TASD Tx Arbitration Start Delay is a...

Page 1698: ...number of available MBs and to the CAN bit rate and inversely proportional to the peripheral clock frequency The optimal arbitration timing is that in which the last MB is scanned just before the fir...

Page 1699: ...he figure above BITRATEN is the CAN bit rate in bits per second calculated by the nominal CAN bit time variables BITRATEF is the CAN bit rate in bits per second calculated by the data CAN bit time var...

Page 1700: ...tion phase 1 Mbaud Table 49 28 TASD values Number of message buffers TASD value Maximum bit rate in data phase MBd 16 24 Invalid 32 24 8 0 Case 2 Clock ratio 1 1 example peripheral clock 40 MHz and os...

Page 1701: ...OTE Asynchronous operation with a 1 1 ratio between peripheral and oscillator clocks is not allowed When doing matching and arbitration FlexCAN needs to scan the whole message buffer memory during the...

Page 1702: ...register can be used instead NumClkNomBit can also be calculated as a function of the expected nominal bit rate used in the arbitration phase NomBitRate as shown in the equation above The number of CA...

Page 1703: ...imum number of peripheral clocks per fast CAN bit for the handshake mechanism to work properly without losing status information through the interface as shown in the equation below MinNumClkFastBitB...

Page 1704: ...The maximum CAN bit rate in the data phase can finally be found DataBitRateMAX 40 x 106 ROUNDUP 6 75 x 40 x 106 50 x 106 6 667 Mbps As demonstrated in this example even though the oscillator clock fre...

Page 1705: ...done during a Permanent Dominant the corresponding acknowledge can never be asserted 49 5 11 1 Freeze mode This mode is requested either by the CPU through the assertion of MCR HALT or when the chip...

Page 1706: ...w power mode is normally used to temporarily disable a complete FlexCAN block with no power consumption It is requested by the CPU through the assertion of MCR MDIS and the acknowledgement is obtained...

Page 1707: ...p Acknowledgement signal The CPU must only consider the FlexCAN in Stop mode when both request and acknowledgement conditions are satisfied If FlexCAN receives the global Stop mode request during Free...

Page 1708: ...Idle state or else waits for the third bit of Intermission and then checks it to be recessive Sets MCR LPM_ACK Requests the shutdown of the CHI submodule clock while keeping the PE submodule clock act...

Page 1709: ...pt flags which are set after entering the current interrupt service routine If the Rx FIFO is enabled MCR RFEN 1 and DMA is disabled MCR DMA 0 the interrupts corresponding to MBs 0 to 7 have different...

Page 1710: ...in access error Read and write access to RAM located positions during Low Power mode results in an access error It is possible for the RXIMR memory region to be considered as general purpose memory a...

Page 1711: ...ow power mode The low power mode should be exited and the clocks resumed before applying soft reset The clock source should be selected when the module is in Disable mode see CTRL1 CLKSRC description...

Page 1712: ...ine the bit rate by programming the PRESDIV field and optionally the EPRESDIV field e Determine the CAN FD bit rate by programming the FPRESDIV field f Determine the internal arbitration mode LBUF 3 I...

Page 1713: ...interfaces Chip Supported debug interfaces IEEE 1149 1 JTAG Serial Wire Debug SWD SWO 4 pin parallel trace port1 WCT1014S Yes Yes Yes No WCT1015S Yes Yes Yes No WCT1016S Yes Yes Yes Yes 1 Overrides th...

Page 1714: ...Miscellaneous Debug Module Access Port Provides centralized control and status registers for an external debugger to control the device ROM Table Identifies which debug IP is available Core Debug Sing...

Page 1715: ...n trace output and a single pin SWO 50 2 CM4 ROM table The ROM table is used to hold the information about the debug components Table 50 3 Bit assignments in the ROM table Bits Name Description 31 12...

Page 1716: ...o SWD mode by the following sequences Once the mode has been changed unused debug pins can be reassigned to any of their alternative muxed functions NOTE For stalled AP transaction reset needs to be i...

Page 1717: ...gister IR codes overlay the Arm JTAG controller IR codes without conflict Refer to the IR codes table for a list of the available IR codes The output of the TAPs TDO are muxed based on the IR code whi...

Page 1718: ...registers Through the Arm Debug Access Port DAP the debugger has access to the status and control elements implemented as registers on the DAP bus as shown in Figure 50 3 These registers provide addi...

Page 1719: ...Select SELECT Read Buffer REBUFF DP Registers 0x00 0x04 0x08 0x0C Data 31 0 A 3 2 RnW DPACC Data 31 0 A 3 2 RnW APACC Debug Port DP Generic See the Arm Debug Interface v5p1 Supplement Debug Port Inter...

Page 1720: ...en the core has halted debug halt mode 9 31 Reserved for future use No 50 6 2 MDM AP Status Register Table 50 9 MDM AP Status Register assignments Bit Name Description 0 Flash memory mass erase acknow...

Page 1721: ...urrent power mode is VLPx This bit is not sticky and should always represent whether VLPx is enabled or not This bit is used by the debugger to throttle JTAG TCK frequency up down 9 10 Reserved Always...

Page 1722: ...accessible and can be monitored to determine when this initial period is completed After this initial period if system reset is held via assertion of the RESET_b pin the debugger has access via the bu...

Page 1723: ...a to a data stream that is captured by a Trace Port Analyzer TPA Table 50 11 WCT101xS TPIU Chip Feature WCT1014S WCT1015S The TPIU in the device supports a limited subset of the full TPIU functionalit...

Page 1724: ...unctionality as soon as the low power mode exits and the system returns to a state with active debug In the case that the debugger logic is powered off the debugger is reset upon recovery and must be...

Page 1725: ...OFF DWT FF FF OFF ETM 2 FF FF OFF 1 Debugger state in STOP1 and STOP2 is same as in STOP 2 Present in WCT1016S only 50 14 Debug and security When security is enabled FSEC SEC 10 the debug port capabil...

Page 1726: ...Debug and security MWCT101xS Series Reference Manual Rev 3 07 2019 1726 NXP Semiconductors...

Page 1727: ...he JTAGC block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode Testing is performed via a boundary scan technique as de...

Page 1728: ...supports several IEEE 1149 1 2001 defined instructions as well as several public and private device specific instructions see JTAGC block instructions for a list of supported instructions Bypass regis...

Page 1729: ...ock supports several IEEE 1149 1 2001 defined test modes A test mode is selected by loading the appropriate instruction into the instruction register when the JTAGC is enabled Supported test instructi...

Page 1730: ...nput Test mode select Weak pullup 1 TDO output buffer enable is negated when the JTAGC is not in the Shift IR or Shift DR states A weak pull may be implemented at the TDO pad for use when JTAGC is ina...

Page 1731: ...I when the TAP controller is in the Shift IR state and latched on the falling edge of TCK in the Update IR state The latched instruction value can only be changed in the Update IR and Test Logic Reset...

Page 1732: ...28 27 26 25 24 23 22 21 20 19 18 17 16 R Part Revision Number Design Center Part Identification Number W Reset PRN DC PIN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Part Identification Number Manufacture...

Page 1733: ...set the TAP controller is forced into the Test Logic Reset state thus disabling the test logic and allowing normal operation of the on chip system logic In addition the instruction register is loaded...

Page 1734: ...s states The value shown next to each state is the value of the TMS signal sampled on the rising edge of the TCK signal As the figure shows holding TMS at logic 1 when clocking TCK through a sufficie...

Page 1735: ...XIT1 DR EXIT1 IR P AUSE DR P AUSE IR EXIT2 IR EXIT2 DR UPDA TE DR UPDA TE IR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 51 4 IEEE 1149 1 2001 TAP controller finite state ma...

Page 1736: ...etails All undefined opcodes are reserved Table 51 4 4 bit JTAG instructions Instruction Code 3 0 Instruction summary IDCODE 0000 Selects device identification register for shift SAMPLE PRELOAD 0010 S...

Page 1737: ...s The SAMPLE portion of the instruction obtains a sample of the system data and control signals present at the MCU input pins and just before the boundary scan register cells at the output pins This s...

Page 1738: ...into the boundary scan register using the SAMPLE PRELOAD instruction before the selection of EXTEST EXTEST asserts the internal system reset for the MCU to force a predictable internal state when perf...

Page 1739: ...lls for each pad are interconnected serially to form a shift register chain around the border of the design The boundary scan register consists of this shift register chain and is connected between TD...

Page 1740: ...Initialization application information MWCT101xS Series Reference Manual Rev 3 07 2019 1740 NXP Semiconductors...

Page 1741: ...requency Added footnote for EEPROM emulated by FlexRAM Data flash D flash emulated EEPROM In Block diagram Added footnote to CSEc In Feature comparison Minor editorial updates Updated the starting par...

Page 1742: ...overview changes Added reference of Devices Generic User Guide In Wake up sources updated table AWIC stop and VLPS wake up sources MCM changes A 9 1 Chip specific MCM information changes Added Note i...

Page 1743: ...A 11 1 Chip specific PORT information changes In Chip specific PORT information Added On this chip the pullup and pulldown enables are controllable Added Finding address for PORTx_PCRn Added Reset pin...

Page 1744: ...tantial content changes MPU changes A 14 1 Chip specific MPU information changes In MPU Logical Bus Master Assignments in table MPU Logical Bus Master Assignments added 4 7 Not implemented A 14 2 MPU...

Page 1745: ...ng and configuring sources for addresses Removed External Signal description section eDMA changes A 17 1 Chip specific eDMA information changes No substantial content changes A 17 2 eDMA2 module chang...

Page 1746: ...how the associated module In TRGMUX register descriptions updated table Select Bit Fields EWM changes A 19 1 Chip specific EWM information changes No substantial content changes A 19 2 EWM module chan...

Page 1747: ...on of each CR and SR changed text reference for range of channels to list of actual implemented channels Updated the register description of SR0 WDOG changes A 22 1 Chip specific WDOG information chan...

Page 1748: ...and example configurations in Internal Clocking Requirements section In Table 25 1 added footnote to PREDIV_SYS_CLK In Table 25 1 added note Configuring DIVSLOW_CLK to lower frequencies In Module cloc...

Page 1749: ...descriptions Updated the register descriptions to show the associated module Clarified the CGC clock gate control bit description A 29 Memories and memory interfaces changes Added SRAM access Behavior...

Page 1750: ...6S In Figure 32 4 64KB E Flash block added to CSEc Enabled and FlexMEM Enabled views and changed 1st Analog Block block to 2 Analog Blocks and deleted 2nd Analog Block block Added MWCT1016S to end of...

Page 1751: ...ing When running any In Flash commands added Data Flash column in table and removed row for 0x03 In Flash commands by mode removed content for NVM Special from table Flash commands by mode In Allowed...

Page 1752: ...and Reset sequence changed MESSAGE_LENGTH to PAGE_LENGTH Fixed typo FlexRAM and Data Flash were swapped in table Flash commands Updated Cryptographic Services Engine CSEc module features QSPI changes...

Page 1753: ...A 36 SMC changes Updated Aborted very low power stop mode entry Updated High Speed Run HSRUN mode for The ratio of frequency between PMC changes A 37 1 Chip specific PMC changes Added LVD LVW and LVR...

Page 1754: ...Gain Register UG Added the description to ADC Status and Control Register 1 SC1AA SC1Z and ADC Data Result Registers RAA RZ CMP changes A 40 1 Chip specific CMP changes In CMP input connections added...

Page 1755: ...bit fields OUTINIT CHnOI Combined bit fields OUTMASK CHnOM Combined bit fields POL POLn Combined bit fields SWOCTRL CHnOCV SWOCTRL CHnOC Combined bit fields PWMLOAD CHnSEL Removed section FlexTimer P...

Page 1756: ...eral clock step and in Also list 2nd bullet Added note While the timer is running CVALn register in Current Timer Value CVAL0 CVAL3 register Updated the figure Programming Model LPTMR changes A 44 1 C...

Page 1757: ...RST Updated the description of CFGR1 OUTCFG CFGR1 PINCFG TCR and TDR LPI2C changes A 47 1 Chip specific LPI2C information changes Updated Instantiation information A 47 2 LPI2C module changes Added n...

Page 1758: ...Minor editorial updates Added Clocking and Resets Removed In the case of a framing error provided the received character from Data sampling technique Added description to the Parameter Register PARAM...

Page 1759: ...itration Phase in one location in CAN FD frames Removed unneeded version of TDC offset configuration equation in Transceiver delay compensation Minor editorial work in Tx arbitration start delay Corre...

Page 1760: ...MWCT101xS Series Reference Manual Rev 3 07 2019 1760 NXP Semiconductors...

Page 1761: ...document is provided solely to enable system and software implementers to use NXP products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated ci...

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