NXP Semiconductors MWCT101 S Series, Reference Manual

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1. For TCM sizes, see MCM chapter. Device specific reset values of LMDR0 and LMDR1 registers are documented in Chip-
specific MCM information.
NOTE
The DFLASH value indicated above for WCT1016S is for non
EEE mode, i.e., complete FlexNVM (512 KB) being used as
DFLASH. For EEE mode, this size will be 448 KB.
30.2 Overview
The Miscellaneous System Control Module (MSCM) contains CPU configuration
registers and on-chip memory controller registers.
The MSCM block diagram is shown below in Figure 30-1 :
CPU Configuration
Registers
On-Chip Memory
Registers
MSCM
Reset Configuration
(RCON)
On-Chip Memory
Bus Int
erf
ace t
o CPU or other Bus Mast
er
s
Figure 30-1. MSCM Block Diagram
30.3 Chip Configuration and Boot
The device’s logical definition is controlled via chip-specific configuration bits,
supported memory sizes and packing options. Collectively, these configuration bits
define a reset configuration value (RCON).
Once the core has fetched the needed reset vector(s), it is expected that core and system
configuration information is read from a globally-accessible slave peripheral that
properly converts the information into more appropriate values. More specifically, the
Overview
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
658 NXP Semiconductors