NXP Semiconductors MWCT101 S Series, Reference Manual

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1. 0.5 to 1.5 FlexIO clock cycles for external pin
2. 1 FlexIO clock cycle for an internally driven pin
For timing considerations such as output valid time and input setup time for specific
applications (SPI Master, SPI Slave, I2C Master, I2S Master, I2S Slave) please refer to
the FlexIO Application Information Section.
48.4.5 Interrupts and DMA Requests
The following table illustrates the status flags that can generate the FlexIO interrupt and
DMA requests.
Table 48-3. FlexIO Interrupts and DMA Requests
Flag Description Interrupt DMA Request Low Power Wakeup
SSF Shifter Status Flag. Y Y Y
SEF Shifter Error Flag. Y N Y
TSF Timer Status Flag. Y N Y
48.4.6 Peripheral Triggers
The connection of the FlexIO peripheral triggers with other peripherals are device
specific.
48.4.6.1 Output Triggers
Each FlexIO Timer generates an output trigger equal to the timer output. The output
trigger is not affected by the timer pin polarity configuration.
48.4.6.2 Input Trigger
FlexIO supports multiple external trigger inputs that can be used to trigger one or more
FlexIO timers. The external triggers are synchronized to the FlexIO functional clock and
must assert for at least two cycles of the FlexIO functional clock to be sampled correctly.
Functional description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1550 NXP Semiconductors