NXP Semiconductors MWCT101 S Series, Reference Manual

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Table 25-1. Clock descriptions
Clock name Related clock selector Related clock divider Description
PREDIV_SYS_C
LK
1
SCG_xCCR[SCS] — Clocks the QSPI memory in HSRUN
80 mode.
CORE_CLK
2
SCG_xCCR[SCS]
SCG_xCCR[DIVCORE]
(÷ 1...16)
Clocks the Arm core, divided by
DIVCORE bits inside SCG.
SYS_CLK
2
SCG_xCCR[SCS]
SCG_xCCR[DIVCORE]
(÷ 1...16)
Clocks the Crossbar, NVIC, Flash
controller, FTM, PDB, and so on.
BUS_CLK SCG_xCCR[SCS]
SCG_xCCR[DIVBUS]
(÷ 1...16)
Clocks the chip peripherals.
FLASH_CLK
3
(SCG_SLOW_CL
K in SCG)
SCG_xCCR[SCS]
SCG_xCCR[DIVSLOW]
(÷ 1...8)
Clocks the flash module.
SPLL_CLK — — Output of PLL (VCO_CLK ÷ 2)
SIRC_CLK — — Output clock of Slow IRC.
FIRC_CLK — — Output clock of Fast IRC.
SOSC_CLK SCG_SOSCCFG[EREFS] — System oscillator clock. Can be either
the EXTAL pin or output of oscillator
(SOSC).
NOTE: ERCLK/OSCERCLK stands
for the same clock source, in
some module chapters.
RTC_CLKOUT — — RTC oscillator output driving external
pin.
LPO32K_CLK SIM_LPOCLKS[CLK32SEL] A fixed divide by 4 of LPO_CLK
drives 01b input of RTC_CLK
multiplexer.
Source clock for RTC.
LPO128K_CLK — — Always on low power oscillator clock
generated by PMC.
SCG_CLKOUT SCG_CLKOUTCNFG[CLKOUT
SEL]
— SCG output clock that can be driven by
SOSC_CLK, SIRC_CLK, FIRC_CLK,
SPLL_CLK, or SCG_SLOW_CLK
(FLASH_CLK).
LPO_CLK SIM_LPOCLKS[LPOCLKSEL] — Clock output generated from one of
three LPO clocks sources
(LPO128K_CLK, LPO32K_CLK,
LPO1K_CLK).
CLKOUT SIM_CHIPCTL[CLKOUTSEL]
SIM_CHIPCTL[CLKOUTDIV]
(÷ 1...8)
Selected from one of eight internal
clock sources.
VCO_CLK — — VCO output clock within PLL. Its
frequency = SPLL_CLK × 2.
SPLLDIV1_CLK —
SCG_SPLLDIV[SPLLDIV1]
(÷ 1, 2, 4, 8, 16, 32, 64, or
output disabled)
Divided SPLL_CLK
This should be configured to 80MHz or
less in RUN mode and to 112 MHz or
less in HSRUN mode.
SPLLDIV2_CLK —
SCG_SPLLDIV[SPLLDIV2]
(÷ 1, 2, 4, 8, 16, 32, 64, or
output disabled)
Divided SPLL_CLK
This should be configured to 40 MHz
or less in RUN mode and 56 MHz or
less in HSRUN mode.
Table continues on the next page...
Chapter 25 Clock Distribution
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 511