NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1536 / 1761

48.3.1.18.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SHIFTBUFBBS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SHIFTBUFBBS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
48.3.1.18.3 Fields
Field Function
31-0
SHIFTBUFBBS
Shift Buffer
Alias to SHIFTBUF register, except reads/writes to this register are bit swapped within each byte. Reads
return { SHIFTBUF[24:31], SHIFTBUF[16:23], SHIFTBUF[8:15], SHIFTBUF[0:7] }.
48.3.1.19 Timer Control N Register (TIMCTL0 - TIMCTL3)
48.3.1.19.1 Offset
Register Offset
TIMCTL0 400h
TIMCTL1 404h
TIMCTL2 408h
TIMCTL3 40Ch
Memory Map and Registers
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1536 NXP Semiconductors