NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1610 / 1761

49.4.2.15.4 Fields
Field Function
31-0
FGM
Rx FIFO Global Mask Bits
These bits mask the ID filter table elements bits in a perfect alignment.
0b - The corresponding bit in the filter is "don’t care."
1b - The corresponding bit in the filter is checked.
49.4.2.16 Rx FIFO Information register (RXFIR)
49.4.2.16.1 Offset
Register Offset
RXFIR 4Ch
49.4.2.16.2 Function
RXFIR provides information on Rx FIFO.
This register is the port through which the CPU accesses the output of the RXFIR FIFO
located in RAM. The RXFIR FIFO is written by the FlexCAN whenever a new message
is moved into the Rx FIFO. Also, its output is updated whenever the output of the Rx
FIFO is updated with the next message. See
Rx FIFO for instructions on reading this
register.
49.4.2.16.3 Diagram
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset
u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 IDHIT
W
Reset
u u u u u u u u u u u u u u u u
Memory map/register definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1610 NXP Semiconductors