NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1140 / 1761

Field Function
If another event occurs between the read and write operations, the write operation has no effect;
therefore, CHF remains set indicating an event has occurred. In this case a CHF interrupt request is not
lost due to the clearing sequence for a previous CHF.
0b - No channel (n) event has occurred.
1b - A channel (n) event has occurred.
6
CHIE
Channel (n) Interrupt Enable
Enables channel (n) interrupt.
0b - Disable channel (n) interrupt. Use software polling.
1b - Enable channel (n) interrupt.
5
MSB
Channel (n) Mode Select
Used on the selection of the channel (n) mode. See Channel Modes .
This field is write protected. It can be written only when MODE[WPDIS] = 1.
4
MSA
Channel (n) Mode Select
Used on the selection of the channel (n) mode. See Channel Modes .
This field is write protected. It can be written only when MODE[WPDIS] = 1.
3
ELSB
Channel (n) Edge or Level Select
Used on the selection of the channel (n) mode. See Channel Modes .
This field is write protected. It can be written only when MODE[WPDIS] = 1.
2
ELSA
Channel (n) Edge or Level Select
Used on the selection of the channel (n) mode. See Channel Modes .
This field is write protected. It can be written only when MODE[WPDIS] = 1.
1
ICRST
FTM counter reset by the selected input capture event.
FTM counter reset is driven by the selected event of the channel (n) in the Input Capture mode.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0b - FTM counter is not reset when the selected channel (n) input event is detected.
1b - FTM counter is reset when the selected channel (n) input event is detected.
0
DMA
DMA Enable
Enables DMA transfers for the channel.
0b - Disable DMA transfers.
1b - Enable DMA transfers.
41.4.3.6 Channel (n) Value (C0V - C7V)
41.4.3.6.1 Offset
For a = 0 to 7:
Register Offset
CaV 10h + (a × 8h)
Memory map and register definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1140 NXP Semiconductors