NXP Semiconductors MWCT101 S Series, Reference Manual

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FTM counter
channel (n) output
(before output mask)
channel (n) output
(after output mask)
the beginning of new PWM cycles
configured PWM signal starts
to be available in the channel (n) output
channel (n) output is disabled
CH(n)OM bit
Figure 41-80. Output mask with POLn = 0
The following table shows the output mask result before the polarity control.
Table 41-14. Output mask result for channel (n) before the polarity control
CH(n)OM Output Mask Input Output Mask Result
0 inactive state inactive state
active state active state
1 inactive state inactive state
active state
41.5.18 Fault Control
The fault control is enabled if FAULTM[1:0] ≠ 0:0.
FTM can have up to four fault inputs. FAULTnEN bit (where n = 0, 1, 2, 3) enables the
fault input n and FFLTRnEN bit enables the fault input n filter. FFVAL[3:0] bits select
the value of the enabled filter in each enabled fault input.
If FLTPS[3:0] = 0, the fault input after being synchronized by FTM input clock is the
filter input.
Functional Description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1246 NXP Semiconductors