NXP Semiconductors MWCT101 S Series, Reference Manual

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The following table gives some examples for typical use cases:
Table 33-23. Access Duration Examples - Bus Clock Side
QSPI_TBCT[WMRK] Number of Bytes per DMA
Loop
1
Number of Bus Clock
cycles for DMA Minor Loop
Time Duration of DMA
Minor Loop for 80Mhz Bus
clock Frequency
3 16 12+4 = 16 ~200ns
7 32 12+8 = 20 ~250ns
11 48 12+12 = 24 ~300ns
15 64 12+16 = 28 ~350ns
19 80 12+20 = 32 ~400ns
1. DMA Loop means one Minor Loop Completion which is equivalent to one.
NOTE
The table figure represents ideal scenario, actual performance
will depend on how the system is integrated.
Serial Flash Device Side (data write):
The number of serial flash cycles can be determined in the following way:
• Number of serial flash clock cycles required to write 16 bytes, corresponding to four
TX Buffer entry(setup of command and address not considered): 8 cycles for Octal
DDR mode (Hyperflash/HyperRAM) instructions in Individual Flash Mode, 32
cycles for Quad SDR writes in individual flash mode.
• Overhead due to clock domain crossing : 1 cycle.
The following table lists the number of clock cycles required to read the data from the
serial flash corresponding to the different settings of the QSPI_TBCT[WMRK] field:
Table 33-24. Access Duration Examples - Serial Flash side
QSPI_TBCT[
WMRK]
setting
Num Bytes
per DMA
Loop
1
Num SCKFx Time duration for
consuming data at Flash
interface 100MHz SCKFx
(10ns period)
2
Time for fifo to get empty
3
IFM
4
Quad IFM Octal
DDR
IFM Quad IFM Octal
DDR
IFM Quad IFM Octal
DDR
3 16 32 8 320ns 80ns 2240ns 560ns
7 32 64 16 640ns 160ns 1920ns 480ns
15 64 128 32 1280ns 320ns 1280ns 320ns
23 96 192 48 1920ns 480ns 640ns 160ns
1. DMA Loop means one Minor loop completion which is equivalent to one Major Loop iteration.
2. Not all flash devices support writes at 100Mhz. Please refer to the flash datasheet for the actual page program frequency
supported.
3. The assumption for these timings is that the TX Fifo was full when the transaction was initiated
4. Individual flash mode.
Chapter 33 Quad Serial Peripheral Interface (QuadSPI)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 911