NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 452 / 1761

20.4.2.1 Optional interrupt notification for non-correctable error
events
The ERM provides an option to generate an interrupt notification upon the report of a
non-correctable ECC event. This sequence describes how to use the option:
1. To enable interrupt notifications for non-correctable error events on Memory n, set
CRx[ENCIEn] to 1.
2. Subsequently, when a non-correctable error event on Memory n is detected, the
ERM:
• Records the event and address as usual.
• Additionally sends an interrupt notification corresponding to the event.
3. To clear both the record of an event and the corresponding interrupt notification,
write 1 to SRx[NCEn] to change its value to 0.
20.5 Initialization
For each ERM channel, prepare the corresponding memory array before enabling ERM
interrupts about errors for that memory.
1. Initialize the memory to a known value so that the correct corresponding ECC
codeword is stored.
2. During the memory's initialization, if the ERM captures information about any ECC
error event, clear the corresponding SRx[SBCn] or SRx[NCEn] field that stores the
record of the event.
3. Program the applicable CRx[ESCIEn] and CRx[ENCIEn] fields to enable ERM
interrupts as desired.
Initialization
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
452 NXP Semiconductors