NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1003 / 1761

Field Function
Field supported in Field not supported in
— ADC0_CFG1
ADC1_CFG1 —
7
—
Reserved
6-5
ADIV
Clock Divide Select
Selects the divide ratio used by the ADC to generate the internal clock ADCK.
00b - The divide ratio is 1 and the clock rate is input clock.
01b - The divide ratio is 2 and the clock rate is (input clock)/2.
10b - The divide ratio is 4 and the clock rate is (input clock)/4.
11b - The divide ratio is 8 and the clock rate is (input clock)/8.
4
—
Reserved
3-2
MODE
Conversion mode selection
Selects the ADC resolution.
00b - 8-bit conversion.
01b - 12-bit conversion.
10b - 10-bit conversion.
11b - Reserved
1-0
ADICLK
Input Clock Select
Selects the input clock source to generate the internal clock, ADCK. See the clock distribution/clocking
chapter of your device for details on which alternate clocks are supported.
00b - Alternate clock 1 (ALTCLK1)
01b - Alternate clock 2 (ALTCLK2)
10b - Alternate clock 3 (ALTCLK3)
11b - Alternate clock 4 (ALTCLK4)
38.4.4 ADC Configuration Register 2 (CFG2)
38.4.4.1 Offset
Register Offset
CFG2 44h
38.4.4.2 Function
Configuration Register 2 (CFG2) selects the long sample time duration during long
sample mode.
Chapter 38 Analog-to-Digital Converter (ADC)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1003