NXP Semiconductors MWCT101 S Series, Reference Manual

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SCG_SPLLCFG field descriptions (continued)
Field Description
Multiplier for the System PLL. The MULT bits establish the multiplication factor applied to the PLL
reference clock frequency.
Table 26-1. PLL VCO Multiply Factor
MULT Multiply
Factor MULT Multiply
Factor MULT Multiply
Factor MULT Multiply
Factor
00000 16 01000 24 10000 32 11000 40
00001 17 01001 25 10001 33 11001 41
00010 18 01010 26 10010 34 11010 42
00011 19 01011 27 10011 35 11011 43
00100 20 01100 28 10100 36 11100 44
00101 21 01101 29 10101 37 11101 45
00110 22 01110 30 10110 38 11110 46
00111 23 01111 31 10111 39 11111 47
15–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10–8
PREDIV
PLL Reference Clock Divider
Selects the amount to divide down the reference clock for the System PLL. The resulting frequency must
be in the range specified in the datasheet.
Table 26-2. System PLL Reference Divide Factor
PREDIV Divide Factor
000 1
001 2
010 3
011 4
100 5
101 6
110 7
111 8
7–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
Reserved
This field is reserved.
This field is reserved. Software should write 0 to this bit to maintain compatibility.
Chapter 26 System Clock Generator (SCG)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 561