NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 720 / 1761

32.4.4.1.2.2 Function
The FSTAT register reports the operational status of the FTFC module.
The CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The
MGSTAT0 bit is read only. The unassigned bits read 0 and are not writable.
NOTE
When set, the Access Error (ACCERR) and Flash Protection
Violation (FPVIOL) bits in this register prevent the launch of
any more commands or writes to the FlexRAM (when
EEERDY is set) until the flag is cleared (by writing a one to it).
32.4.4.1.2.3 Diagram
Bits 7 6 5 4 3 2 1 0
R
CCIF
RDCOLER R
ACCERR
FPVIOL
0
MGSTAT0
W
W1C W1C W1C W1C
Reset 1 0 0 0 0 0 0 0
32.4.4.1.2.4 Fields
Field Function
7
CCIF
Command Complete Interrupt Flag
The CCIF flag indicates that an FTFC/CSEc command or emulated EEPROM file system operation has
completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command, and CCIF stays low
until command completion or command violation. The CCIF flag is also cleared by a successful write to
FlexRAM while enabled for EEE, and CCIF stays low until the emulated EEPROM file system has
created the associated EEPROM data record. The CCIF flag will also clear upon execution of any CSEc
command,and will set upon completion.
The CCIF bit is reset to 0 but is set to 1 by the memory controller at the end of the reset initialization
sequence. Depending on how quickly the read occurs after reset release, the user may or may not see
the 0 hardware reset value.
0b - FTFC command or emulated EEPROM file system operation in progress
1b - FTFC command or emulated EEPROM file system operation has completed
6
RDCOLERR
FTFC Read Collision Error Flag
The RDCOLERR error bit indicates that the MCU attempted a read from an FTFC resource that was
being manipulated by an FTFC command (CCIF=0). Any simultaneous access is detected as a collision
error by the block arbitration logic. The read data in this case cannot be guaranteed. The RDCOLERR bit
is cleared by writing a 1 to it. Writing a 0 to RDCOLERR has no effect.
0b - No collision error detected
Table continues on the next page...
Memory map and registers
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
720 NXP Semiconductors