NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 721 / 1761

Field Function
1b - Collision error detected
5
ACCERR
Flash Access Error Flag
The ACCERR error bit indicates an illegal access has occurred to an FTFC resource caused by a
violation of the command write sequence or issuing an illegal FTFC command. While ACCERR is set, the
CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to
ACCERR while CCIF is set. Writing a 0 to the ACCERR bit has no effect.
0b - No access error detected
1b - Access error detected
4
FPVIOL
Flash Protection Violation Flag
The FPVIOL error bit indicates an attempt was made to program or erase an address in a protected area
of program flash or data flash memory during a command write sequence or a write was attempted to a
protected area of the FlexRAM while enabled for emulated EEPROM. While FPVIOL is set, the CCIF flag
cannot be cleared to launch a command. The FPVIOL bit is cleared by writing a 1 to FPVIOL while CCIF
is set. Writing a 0 to the FPVIOL bit has no effect.
0b - No protection violation detected
1b - Protection violation detected
3-1
—
Reserved
0
MGSTAT0
Memory Controller Command Completion Status Flag
The MGSTAT0 status flag is set if an error is detected during execution of an FTFC command or during
the flash reset sequence. As a status flag, this bit cannot (and need not) be cleared by the user like the
other error flags in this register.
The value of the MGSTAT0 bit for "command-N" is valid only at the end of the "command-N" execution
when CCIF=1 and before the next command has been launched. At some point during the execution of
"command-N+1," the previous result is discarded and any previous error is cleared.
32.4.4.1.3 Flash Configuration Register (FCNFG)
32.4.4.1.3.1 Offset
Register Offset
FCNFG 1h
32.4.4.1.3.2 Function
This register provides information on the current functional state of the FTFC module.
The erase control bits (ERSAREQ and ERSSUSP) have write restrictions. RAMRDY,
and EEERDY are read-only status bits. The reset values for the RAMRDY, and
EEERDY bits are determined during the reset sequence.
Chapter 32 Flash Memory Module (FTFC)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 721