NXP Semiconductors MWCT101 S Series, Reference Manual, Page: 1650 / 1761

1 = Indicates the current MB may have a remote request frame to be transmitted if MB is
Tx. If the MB is Rx then incoming remote request frames may be stored.
0 = Indicates the current MB has a data frame to be transmitted. In Rx MB it may be
considered in matching processes.
NOTE
When configuring CAN FD frames, the RTR bit must be
negated.
DLC — Length of Data in Bytes
This 4-bit field is the length (in bytes) of the Rx or Tx data, which is located in offset 0x8
through 0xF of the MB space (see
Table 49-9 ). In reception, this field is written by the
FlexCAN module, copied from the DLC (Data Length Code) field of the received frame.
In transmission, this field is written by the CPU and corresponds to the DLC field value
of the frame to be transmitted. When RTR = 1, the frame to be transmitted is a remote
frame and does not include the data field, regardless of the DLC field (see
Table 49-12 ).
TIME STAMP — Free-Running Counter Time Stamp
This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at
the time when the beginning of the Identifier field appears on the CAN bus.
PRIO — Local priority
This 3-bit field is used only when MCR[LPRIO_EN] is set, and it only makes sense for
Tx mailboxes. These bits are not transmitted. They are appended to the regular ID to
define the transmission priority. See
Arbitration process .
ID — Frame Identifier
In standard frame format, only the 11 most significant bits (28 to 18) are used for frame
identification in both receive and transmit cases. The 18 least significant bits are ignored.
In extended frame format, all bits are used for frame identification in both receive and
transmit cases.
DATA BYTE 0 to 63 — Data Field
Up to sixty four bytes can be used for a data frame, depending on the size of payload
selected for the message buffers.
For Rx frames, the data is stored as it is received from the CAN bus. DATA BYTE (n) is
valid only if n is less than DLC as shown in the table below.
Memory map/register definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1650 NXP Semiconductors