NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1599 / 1761

49.4.2.10.4 Fields
Field Function
31-0
BUF31TO0M
Buffer MB i Mask
Each bit enables or disables the corresponding FlexCAN message buffer interrupt for MB31 to MB0.
NOTE: Setting or clearing a bit in the IMASK1 Register can assert or negate an interrupt request, if the
corresponding IFLAG1 bit is set.
0b - The corresponding buffer interrupt is disabled.
1b - The corresponding buffer interrupt is enabled.
49.4.2.11 Interrupt Flags 1 register (IFLAG1)
49.4.2.11.1 Offset
Register Offset
IFLAG1 30h
49.4.2.11.2 Function
This register defines the flags for the 32 message buffer interrupts for MB31 to MB0. It
contains one interrupt flag bit per buffer. Each successful transmission or reception sets
the corresponding IFLAG1 bit. If the corresponding IMASK1 bit is set, an interrupt will
be generated. The interrupt flag must be cleared by writing 1 to it. Writing 0 has no
effect. There is an exception when DMA for Rx FIFO is enabled, as described below.
The BUF7I to BUF5I flags are also used to represent FIFO interrupts when the Rx FIFO
is enabled. When MCR[RFEN] is set and MCR[DMA] is negated, the function of the
eight least significant interrupt flags changes: BUF7I, BUF6I, and BUF5I indicate
operating conditions of the FIFO , BUF0I is used to empty FIFO, and BUF4I to BUF1I
bits are reserved.
Before enabling MCR[RFEN], the CPU must service the IFLAG bits asserted in the Rx
FIFO region; see
Rx FIFO . Otherwise, these IFLAG bits will mistakenly show the related
MBs now belonging to FIFO as having contents to be serviced. When MCR[RFEN] is
negated, the FIFO flags must be cleared. The same care must be taken when a
CTRL2[RFFN] value is selected, extending Rx FIFO filters beyond MB7. For example,
when RFFN is 0x8, the MB0–23 range is occupied by Rx FIFO filters and related IFLAG
bits must be cleared.
Chapter 49 FlexCAN
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1599