NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 862 / 1761

QuadSPI_SR field descriptions (continued)
Field Description
22–20
Reserved
This field is reserved.
19
RXFULL
RX Buffer Full. Asserted when the RX Buffer is full, i.e. that QSPI_RBSR[RDBFL] field is equal to 32.
18–17
Reserved
This field is reserved.
16
RXWE
RX Buffer Watermark Exceeded. Asserted when the number of valid entries in the RX Buffer exceeds the
number given in the QSPI_RBCT[WMRK] field.
15
Reserved
This field is reserved.
14
AHB3FUL
AHB 3 Buffer Full. Asserted when AHB 3 buffer is full.
13
AHB2FUL
AHB 2 Buffer Full. Asserted when AHB 2 buffer is full.
12
AHB1FUL
AHB 1 Buffer Full. Asserted when AHB 1 buffer is full.
11
AHB0FUL
AHB 0 Buffer Full. Asserted when AHB 0 buffer is full.
10
AHB3NE
AHB 3 Buffer Not Empty. Asserted when AHB 3 buffer contains data.
9
AHB2NE
AHB 2 Buffer Not Empty. Asserted when AHB 2 buffer contains data.
8
AHB1NE
AHB 1 Buffer Not Empty. Asserted when AHB 1 buffer contains data.
7
AHB0NE
AHB 0 Buffer Not Empty. Asserted when AHB 0 buffer contains data.
6
AHBTRN
AHB Access Transaction pending. Asserted when there is a pending request on the AHB interface. Refer
to the AMBA specification for details.
5
Reserved
This field is reserved.
4
Reserved
This field is reserved.
3
RESERVED
This field is reserved.
2
AHB_ACC
AHB Access. Asserted when the transaction currently executed was initiated by AHB bus.
1
IP_ACC
IP Access. Asserted when transaction currently executed was initiated by IP bus.
0
BUSY
Module Busy. Asserted when module is currently busy handling a transaction to an external flash device.
Memory Map and Register Definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
862 NXP Semiconductors