NXP Semiconductors MWCT101 S Series, Reference Manual, Page: 931 / 1761

34.4 Clocking modes
The following sections describe the supported clocking modes on this chip.
34.4.1 Clock gating
To conserve power, most module clocks can be turned off by configuring the CGC field
of the peripheral control registers in the PCC module. These fields are cleared after any
reset, which disables the Protocol clock of the corresponding module. Before initializing
a module, the corresponding field in the PCC peripheral control register needs to be set to
enable the module clock. Be sure to disable the module before turning off the clock (see
Clock Distribution and PCC for details).
34.4.2 Stop mode options
This chip has two Stop modes:
• STOP1
• STOP2
See the STOPO field in Stop Control Register (SMC_ STOPCTRL ) for more details.
When configured for STOP1, the core clocks, system clocks, and bus clocks are all gated.
When configured for STOP2, only the core and system clocks are gated, but the bus
clock remains active. The bus masters and bus slaves clocked by the system clock enter
Stop mode, but the bus slaves clocked by the bus clock remain in Run mode. The clock
generators in the SCG and the PMC's on-chip regulator also remain in Run mode. The
following can initiate an exit from STOP.
• Reset
• An asynchronous interrupt from a bus master (valid for STOP1)
• A synchronous interrupt from a bus slave clocked by the bus clock (valid for STOP2)
If configured, a DMA request (using the asynchronous DMA wake-up) can also be used
to exit Stop for the duration of a DMA transfer before the chip transitions back into
STOP2.
34.4.3 DMA wake-up
Chapter 34 Power Management
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 931