NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 949 / 1761

35.3.5 Stop Control Register (SMC_ STOPCTRL )
The STOPCTRL register provides various control bits allowing the user to fine tune
power consumption during the stop mode selected by the STOPM field.
NOTE
This register is reset on Chip POR and by reset types that
trigger Chip POR. It is unaffected by reset types that do not
trigger Chip POR. See the Reset section details for more
information.
Address: 4007_E000h base + 10h offset = 4007_E010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
STOPO
0 0
Reserved
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
SMC_STOPCTRL field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–6
STOPO
Stop Option
These bits control stop operation when STOPM=STOP. When entering Stop mode from RUN mode, the
PMC, SCG and flash remain fully powered, allowing the device to wakeup almost instantaneously at the
expense of higher power consumption. In STOP2, only system clocks are gated allowing peripherals
running on bus clock to remain fully functional. In STOP1, both system and bus clocks are gated.
00 Reserved
Table continues on the next page...
Chapter 35 System Mode Controller (SMC)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 949