NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1759 / 1761

A.50.2 FlexCAN3_FD module changes
• In FlexCAN memory mapping , added a note :"An invalid register access will result in a bus error. This includes reading
a write-only register, writing a read-only register or accessing an invalid address."
• Added note 'See the clock distribution chapter ... ' in CTRL1[CLKSRC] bit field
• Deleted note in CTRL1 register that states 'The user must ensure bit time settings and protocol engine tolerance are in
compliance with the CAN Protocol standard (ISO 11898-1)'
• In Matching process :Added 'For enhanced Rx FIFO refer to Enhanced Rx FIFO'
• Editorial changes throughout the chapter
• Changed “Arbitration Field” to “Arbitration Phase” in one location in
CAN FD frames
• Removed unneeded version of TDC offset configuration equation in Transceiver delay compensation
• Minor editorial work in Tx arbitration start delay
• Corrected formula for BITRATEF in Tx arbitration start delay
• Minor editorial work in field description of RXMGMASK[MG]
• Added note "It is strongly recommended that all ... " in 'Transmit process'
• Added new item ("If MCR[FDEN] is enabled, general purpose memory ...") to list of rules in
Bus interface
A.51 Debug changes
• In Introduction : Added row for note 'Breakpoint and Watchpoint unit' in table 'Debug component description
JTAGC changes
A.52.1 Chip-specific JTAGC information changes
• No substantial content changes
A.52.2 JTAGC module changes
• No substantial content changes
A.52
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1759