NXP Semiconductors MWCT101 S Series, Reference Manual

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41.4.3.25.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CH7OCV CH6OCV CH5OCV CH4OCV CH3OCV CH2OCV CH1OCV CH0OCV
CH7OC CH6OC CH5OC CH4OC CH3OC CH2OC CH1OC CH0OC
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
41.4.3.25.4 Fields
Field Function
31-16
—
Reserved
15-8
CHnOCV
Channel n Software Output Control Value
0b - The software output control forces 0 to the channel output.
1b - The software output control forces 1 to the channel output.
7-0
CHnOC
Channel n Software Output Control Enable
0b - The channel output is not affected by software output control.
1b - The channel output is affected by software output control.
41.4.3.26 FTM PWM Load (PWMLOAD)
41.4.3.26.1 Offset
Register Offset
PWMLOAD 98h
41.4.3.26.2 Function
Enables the reload of the MOD, HCR, CNTIN, C(n)V, and C(n+1)V registers with the
values of their write buffers when the FTM counter changes from the MOD register value
to its next value or when a channel (j) match occurs. A match occurs for channel (j) when
FTM counter = C(j)V. A reload can also occurs when FTM counter = HCR register at a
half cycle match. This register also controls the local and global load mechanisms.
Chapter 41 FlexTimer Module (FTM)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1177