NXP Semiconductors MWCT101 S Series, Reference Manual

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31.1.1 FMC masters
For master port assignments, see Crossbar Switch master assignments .
31.1.2 Program flash and Data flash port width
For Program flash and Data flash port widths, see Flash memory sizes .
31.2 Introduction
The Flash Memory Controller (FMC) is a memory acceleration unit that provides:
• an interface between the device and the dual-bank nonvolatile memory. Bank 0
consists of program flash memory, and bank 1 consists of FlexNVM.
• buffers that can accelerate flash memory and FlexNVM data transfers.
31.2.1 Overview
The Flash Memory Controller manages the interface between the device and the dual-
bank flash memory. The Program Flash is referred as Bank 0 and the Data Flash is
referred as Bank 1. The FMC receives status information detailing the configuration of
the memory and uses this information to ensure a proper interface. The following table
shows the supported read/write operations.
Flash memory type Read Write
Program flash memory 8-bit, 16-bit, and 32-bit reads —
1
FlexNVM used as Data flash memory 8-bit, 16-bit, and 32-bit reads —
1
FlexNVM and FlexRAM used as
emulated EEPROM 8-bit, 16-bit, and 32-bit reads 8-bit, 16-bit, and 32-bit writes
1. A write operation to program flash memory or to FlexNVM used as data flash memory results in a bus error.
In addition, for bank 0 and bank 1, the FMC provides separate mechanisms for
accelerating the interface between the device and the flash memory. A 128 (64 for bank1,
Data Flash)-bit speculation buffer can prefetch the next 128 (64 for bank1, Data Flash)-
bit flash memory location, and a single-entry 128 (64 for bank1, Data Flash)-bit buffer
can store previously accessed flash memory or FlexNVM data for quick access times.
31.2.2 Features
The FMC's features include:
Introduction
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
692 NXP Semiconductors