NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 193 / 1761

11.3.1.8.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
PID
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PID
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.3.1.8.4 Fields
Field Function
31-0
PID
Port Input Disable
0b - Pin is configured for General Purpose Input, provided the pin is configured for any digital
function.
1b - Pin is not configured as General Purpose Input. Corresponding Port Data Input Register bit will
read zero.
11.4 Functional description
11.4.1 General-purpose input
The logic state of each pin is available via the Port Data Input registers, provided the
corresponding bit in the port input enable register is set, the pin is configured for a digital
function and the corresponding Port Control and Interrupt module is enabled.
The input pin synchronizers are shared with the Port Control and Interrupt module, so
that if the corresponding Port Control and Interrupt module is disabled, then
synchronizers are also disabled. This reduces power consumption when a port is not
required for general-purpose input functionality.
11.4.2 General-purpose output
The logic state of each pin can be controlled via the port data output registers and port
data direction registers, provided the pin is configured for the GPIO function. The
following table depicts the conditions for a pin to be configured as input/output.
Chapter 11 General-Purpose Input/Output (GPIO)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 193