NXP Semiconductors MWCT101 S Series, Reference Manual

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Table 2-1. Device feature summary (continued)
Feature Summary for WCT101xS product series
4 word FIFO support on LPI
2
C0
DMA support
1 Mbps ability (even with maximum I
2
C bus loading of 400 pF)
Only high-drive pins are able to support 1 Mbps
Low Power UART (LPUART0–LPUART2) Up to 3 LPUART
Supports LIN protocol versions 1.3, 2.0, 2.1, 2.2A, and SAE
J2602
Standard features
Configurable from 4x to 32x oversampling
Functional in STOP/VLPS modes
LIN slave operation support
32-bit data width
All LPUARTs support DMA and 4-word FIFO
1. HSRUN mode is limited to a maximum ambient temperature of 105°C T
A
2. CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this use case is not
allowed to execute simultaneously. The device need to switch to RUN mode (80 Mhz) to execute CSEc (Security) or
EEPROM writes/erase.
3. On this device, NXP's system MPU implements the safety mechanisms to prevent masters from accessing restricted
memory regions. This system MPU provides memory protection at the level of the Crossbar Switch. Each Crossbar master
(Core, DMA) can be assigned different access rights to each protected memory region. The Arm M4 core version in this
family does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory accesses. In
this document, the term MPU refers to NXP’s system MPU.
2.4 Block diagram
The following figure shows block diagram of the WCT101xS product series.
Chapter 2 Introduction
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 55