NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 288 / 1761

Offset Register Width
(In bits)
Access Reset value
0h - Fh Channel Configuration register (CHCFG0 - CHCFG15) 8 RW 00h
15.3.1.2 Channel Configuration register (CHCFG0 - CHCFG15)
15.3.1.2.1 Offset
For a = 0 to 15:
Register Offset
CHCFGa 0h + (a × 1h)
15.3.1.2.2 Function
Each of the DMA channels can be independently enabled/disabled and associated with
one of the DMA slots (peripheral slots or always-on slots) in the system.
NOTE
Setting multiple CHCFG registers with the same source value
will result in unpredictable behavior. This is true, even if a
channel is disabled (ENBL==0).
Before changing the trigger or source settings, a DMA channel
must be disabled via CHCFGn[ENBL].
15.3.1.2.3 Diagram
Bits 7 6 5 4 3 2 1 0
R
ENB L
TRIG
SOURC E
W
Reset 0 0 0 0 0 0 0 0
Memory map/register definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
288 NXP Semiconductors