NXP Semiconductors MWCT101 S Series, Reference Manual, Page: 638 / 1761

To minimize the quantity of control information stored, the spatial locality property is
used to group several locations together under the same tag. This logical block is
commonly known as a cache line.
When data is loaded into a cache, access times for subsequent loads and stores are
reduced, resulting in overall performance benefits. An access to information already in a
cache is known as a cache hit, and other accesses are called cache misses.
Normally, caches are self-managing, with the updates occurring automatically. Whenever
the processor wants to access a cacheable location, the cache is checked. If the access is a
cache hit, the access occurs immediately. Otherwise, a location is allocated and the cache
line is loaded from memory. Different cache topologies and access policies are possible.
However, they must comply with the memory coherency model of the underlying
architecture.
Caches introduce a number of potential problems, mainly because of:
• memory accesses occurring at times other than when the programmer would
normally expect them,
• the existence of multiple physical locations where a data item can be held.
The local memory controller supports the following modes of operation:
1. Write-through — access to address spaces with this cache mode are cacheable.
• If all cacheable spaces are read-only spaces, the cache will contain read-only
data and all write to the cache will fault. See the chip-specific cacheable space
information.
• A write-through read miss on the input bus causes a line read on the output bus
of a 16-byte-aligned memory address containing the desired address. This miss
data is loaded into the cache and is marked as valid and not modified.
• A write-through read hit to a valid cache location returns data from the cache
with no output bus access.
• A write-through write miss bypasses the cache and writes to the output bus (no
allocate on write miss policy for write-through mode spaces).
• A write-through write hit updates the cache hit data and writes to the output bus.
• The caches are processor-local and do not support hardware cache coherency. If
the processor has accessed write-through regions and an external bus master
(such as DMA) then needs update these regions, software must first perform
explicit cache clears to any needed cache memory range to ensure all modified
cache lines update their associated memories before being modified by external
masters and subsequent processor accesses will get the updated memory.
2. Non-cacheable — access to address spaces with this cache mode are not cacheable.
These accesses bypass the cache and access the output bus.
Introduction
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
638 NXP Semiconductors