NXP Semiconductors MWCT101 S Series, Reference Manual

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Receive data supports a receive data match function that can match received data against
one of two words or against a masked data word. The data match function can also be
configured to compare only the first one or two received data words since the start of the
frame.
• Received data that is already discarded (because the Receive Data Mask
TCR[RXMSK] is set) cannot cause the data match to set, and will delay the match on
the first received data word, until all discarded data is received.
• The receiver match function can also be configured to discard all received data until
a data match is detected, using the Receive Data Match Only CFGR0[RDMO] bit.
• After a receive data match, to allow all subsequent data to be received, first clear the
Receive Data Match Only CFGR0[RDMO] bit, then clear the Data Match Flag
SR[DMF] bit.
45.4.3.3 Clocked Interface
The LPSPI module supports interfacing to external masters that provide only clock and
data pins (LPSPI_PCS is not required). This interface requires:
• using Clock Phase TCR[CPHA] = 1 (data is changed on the leading edge of SCK and
captured on the following edge)
• configuring the LPSPI_PCS input to be always asserted (configure the Peripheral
Chip Select Polarity CFGR1[PCSPOL[n]] = 1). For example, to configure PCS[0] to
be always asserted, set PCSPOL[0] = 1, and don’t configure PCS[0] in the pin
muxing.
• setting the Automatic PCS CFGR1[AUTOPCS] bit = 1 (Automatic PCS generation
is enabled). When Automatic PCS generation (AUTOPCS) is set, a minimum of 4
LPSPI functional clock cycles (divided by PRESCALE configuration) is required
between the last LPSPI_SCK edge of one word and the first LPSPI_SCK edge of the
next word.
45.4.4 Interrupts and DMA Requests
The next table lists the slave mode sources (status flags) that can generate LPSPI
interrupts and LPSPI slave transmit/receive DMA requests.
Functional description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1406 NXP Semiconductors