NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 186 / 1761

NOTE
Not all pins within each port are implemented on each device.
See the chapter on signal multiplexing for the number of GPIO
ports available in the device.
11.3 Memory map and register definition
The registers for each GPIO port occupy 64-byte of the memory map. Any read or write
access to the GPIO slot outside this space results in a bus error.
NOTE
For simplicity, each GPIO port's registers appear with the same
width of 32 bits, corresponding to 32 pins. The actual number
of pins per port (and therefore the number of usable control bits
per port register) is chip-specific. Refer to the chip-specific
GPIO information to see the exact control bits for each port.
11.3.1 GPIO register descriptions
11.3.1.1 GPIO Memory map
GPIOA base address: 400F_F000h
GPIOB base address: 400F_F040h
GPIOC base address: 400F_F080h
GPIOD base address: 400F_F0C0h
GPIOE base address: 400F_F100h
Offset Register Width
(In bits)
Access Reset value
0h Port Data Output Register (PDOR) 32 RW 0000_0000h
4h Port Set Output Register (PSOR) 32 WORZ 0000_0000h
8h Port Clear Output Register (PCOR) 32 WORZ 0000_0000h
Ch Port Toggle Output Register (PTOR) 32 WORZ 0000_0000h
10h Port Data Input Register (PDIR) 32 RO 0000_0000h
Table continues on the next page...
Memory map and register definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
186 NXP Semiconductors