NXP Semiconductors MWCT101 S Series, Reference Manual

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FTM input clock
FTM counter
CnV register
CHF bit
Note:
PS[2:0] = 3'b000
channel (n) in input capture mode with capture only on rising edges
CHnFVAL[3:0] = 4'h1 (channel (n) input filter is enabled)
FLTPS[3:0] = 4'h2 (divide by 3)
53
channel (n) input
54 55 56 57 58 59 60 61 62 63 64 65
4 rising edges of FTM input clock + (1 + 4 x CHnFVAL) rising edges of FTM filter clock =
4 rising edges of FTM input clock + 5 rising edges of FTM filter clock
70 xx
FTM filter clock
66 67 68 69 70 71
2 rising edges
of FTM input clock
(1 + 4 x CHnFVAL) = 5 rising edges of FTM filter counter 2 rising edges
of FTM input clock
Figure 41-19. Example of Channel Input Filter when FLTPS[3:0] ≠ 0
41.5.5.2 FTM Counter Reset in Input Capture Mode
If the channel (n) is in input capture mode and CnSC[ICRST = 1], then when the selected
input capture event occurs in the channel (n) input signal, the current value of the FTM
counter is captured into the CnV register, the CHF bit is set, the channel (n) interrupt is
generated (if CHIE = 1) and the FTM counter is reset to the CNTIN register value.
This allows the FTM to measure a period/pulse being applied to the channel (n) input
(number of the FTM input clocks) without having to implement a subtraction calculation
in software subsequent to the event occurring.
The figure below shows the FTM counter reset when the selected input capture event is
detected in a channel in input capture mode with ICRST = 1.
Functional Description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1202 NXP Semiconductors