NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 275 / 1761

14.3.1.15.2 Function
Each OPACR register consists of eight 4-bit OPACR fields. Each OPACR field defines
the access levels for a particular off-platform peripheral. The peripheral assignment to
each OPACR field is defined by the memory map slot of the peripheral. See the chip-
specific AIPS information for the field assignment of a particular peripheral.
14.3.1.15.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 0
SP2 WP2 TP2
0
SP3 WP3 TP3
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
SP4 WP4 TP4
0 0
SP6 WP6 TP6
0
SP7 WP7 TP7
W
Reset
0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0
14.3.1.15.4 Fields
Field Function
31-28
—
Reserved
27-24
—
Reserved
23
—
Reserved
22
SP2
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPR
x [MPL n ] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0b - This peripheral does not require supervisor privilege level for accesses.
1b - This peripheral requires supervisor privilege level for accesses.
21
WP2
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0b - This peripheral allows write accesses.
1b - This peripheral is write protected.
20
TP2
Trusted Protect
Table continues on the next page...
Chapter 14 Peripheral Bridge (AIPS-Lite)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 275