NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1322 / 1761

The channels are chained by setting the CHAIN bit in corresponding channel's
TCTRL
CHn
register. When a channel is chained, that channel's timer decrements on
previous channel's timeout pulse, regardless of the timer mode (MODE bits). The TSOT
bit does not have any effect if the channel timer (Channel 'n') is chained to previous
channel's timer (Channel 'n-1').
42.5.6 Detailed timing
NOTE
The timing diagrams in these sections are not cycle-accurate
(i.e., some cycles may not be shown), but the timing diagrams
do show the timer channel behavior across several clock cycles.
Table 42-7. Timing diagrams list
Mode Timing Diagram TSOT TROT TSOI CHAIN
32-bit periodic
counter (compare
mode) 00 Figure 42-5 0 0 0 0
Figure 42-6 0 0 1 0
Figure 42-7 0 1 0 0
Figure 42-8 0 1 1 0
Figure 42-9 1 0 0 0
Figure 42-10 1 0 1 0
Figure 42-11 1 1 0 0
Figure 42-12 1 1 1 0
16-bit dual periodic
counter (compare
mode) 01 Figure 42-13 0 0 0 0
32-bit trigger
accumulator mode 10 Figure 42-14 X X 0 0
Figure 42-15 X X 1 0
32-bit trigger capture
mode 11 Figure 42-16 X 0 0 0
Figure 42-17 X 1 0 0
Figure 42-18 X 0 1 0
Timer chaining:
effects on timing
operations - Figure 42-19 - - - -
Functional description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1322 NXP Semiconductors