NXP Semiconductors MWCT101 S Series, Reference Manual

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Field Function
10001b - Oversampling ratio of 18.
10010b - Oversampling ratio of 19.
10011b - Oversampling ratio of 20.
10100b - Oversampling ratio of 21.
10101b - Oversampling ratio of 22.
10110b - Oversampling ratio of 23.
10111b - Oversampling ratio of 24.
11000b - Oversampling ratio of 25.
11001b - Oversampling ratio of 26.
11010b - Oversampling ratio of 27.
11011b - Oversampling ratio of 28.
11100b - Oversampling ratio of 29.
11101b - Oversampling ratio of 30.
11110b - Oversampling ratio of 31.
11111b - Oversampling ratio of 32.
23
TDMAE
Transmitter DMA Enable
TDMAE configures the transmit data register empty flag, STAT[TDRE], to generate a DMA request.
0b - DMA request disabled.
1b - DMA request enabled.
22
—
Reserved
21
RDMAE
Receiver Full DMA Enable
RDMAE configures the receiver data register full flag, STAT[RDRF], to generate a DMA request.
0b - DMA request disabled.
1b - DMA request enabled.
20
RIDMAE
Receiver Idle DMA Enable
RIDMAE configures the receiver idle flag, STAT[IDLE], to generate a DMA request. When this bit is set,
reading the DATA register when either DATA[RXEMPT] or DATA[IDLINE] bit is set, will generate an End
Of Packet response until the completion of the existing DMA transfer. During an End of Packet response,
reading the DATA register will return 0x0000_33FF and does not pull data from the FIFO.
0b - DMA request disabled.
1b - DMA request enabled.
19-18
MATCFG
Match Configuration
Configures the match addressing mode used. This field should only be changed when the transmitter and
receiver are both disabled.
00b - Address Match Wakeup
01b - Idle Match Wakeup
10b - Match On and Match Off
11b - Enables RWU on Data Match and Match On/Off for transmitter CTS input
17
BOTHEDGE
Both Edge Sampling
Enables sampling of the received data on both edges of the baud rate clock, effectively doubling the
number of times the receiver samples the input data for a given oversampling ratio. This bit must be set
for oversampling ratios between x4 and x7 and is optional for higher oversampling ratios. This bit should
only be changed when the receiver is disabled.
0b - Receiver samples input data using the rising edge of the baud rate clock.
1b - Receiver samples input data using the rising and falling edge of the baud rate clock.
16
RESYNCDIS
Resynchronization Disable
When set, disables the resynchronization of the received data word when a data one followed by data
zero transition is detected. This bit should only be changed when the receiver is disabled.
0b - Resynchronization during received data word is supported
1b - Resynchronization during received data word is disabled
Table continues on the next page...
Register definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1478 NXP Semiconductors