NXP Semiconductors MWCT101 S Series, Reference Manual

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From these inputs, the complete transaction is built when the
QSPI_IPCR[SEQID] field is written. The transaction related to the read access
starts and the requested number of bytes is fetched from the external serial flash
device into the RX Buffer. Since the read access is triggered by an IP command,
the IP_ACC status bit and the BUSY bit are both set (both are located in the
Status Register (QSPI_SR) ). A count of the number of entries currently in the
Rx Buffer can be obtained from QSPI_RBSR[RDBFL].
The communication with the external serial flash is stopped when the specified
number of bytes has been read (successful completion of the transaction).
• AHB Command Read: For reading flash data into the AHB Buffer the user
must set up a read access by a master to the address range in the system memory
map which the external serial flash devices are mapped to. The user should
program the QSPI_SFACR[CAS], if required, to desired value else to 0. The
user should also program the buffer registers corresponding to the AHB master
initiating the request, this is depends on the configuration of the
QSPI_RBCT[RXBRD]. The user should provide the correct sequence ID into
the buffer generic configuration register (QSPI_BFGENCR). It is the
responsibility of the software to ensure that a correct read sequence in
programmed in the LUT in accordance with the serial flash device connected on
board. Flash device selection and access mode are determined by the address
accessed in the AHB address space associated to the QuadSPI module (refer to
Memory Mapped Serial Flash Data - Individual Flash Mode on Flash A ,
Memory Mapped Serial Flash Data - Individual Flash Mode on Flash B
On each AHB read access to the memory mapped area the valid data in the AHB
Buffer is checked against the address requested in the actual read. When the
AHB read request can't be served from the content of the AHB Buffer, the buffer
is flushed and the sequence pointed to by the sequence ID is executed by the
controller. The requested number of buffer entries defined in the
QSPI_BUFxCR[ADATSZ] field is then fetched from the external serial flash
device into the internal AHB Buffer. Since the read access is triggered via the
AHB bus, the QSPI_SR[AHB_ACC] status bit is set driving in turn the
QSPI_SR[BUSY] bit until the transaction is finished. The communication with
the external serial flash is stopped when the specified number of entries has been
filled.
2. Data Transfer from the QuadSPI Module Internal Buffers
Functional Description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
896 NXP Semiconductors