NXP Semiconductors MWCT101 S Series, Reference Manual

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QuadSPI_MCR field descriptions (continued)
Field Description
23–20
Reserved
This field is reserved.
19
ISD3FB
Idle Signal Drive IOFB[3] Flash B. This bit determines the logic level the IOFB[3] output of the QuadSPI
module is driven to in the inactive state. Refer to
Driving Flash Control Signals in Single and Dual Mode .
0 IOFB[3] is driven to logic L
1 IOFB[3] is driven to logic H
18
ISD2FB
Idle Signal Drive IOFB[2] Flash B. This bit determines the logic level the IOFB[2] output of the QuadSPI
module is driven to in the inactive state. Refer to
Driving Flash Control Signals in Single and Dual Mode .
0 IOFB[2] is driven to logic L
1 IOFB[2] is driven to logic H
17
ISD3FA
Idle Signal Drive IOFA[3] Flash A. This bit determines the logic level the IOFA[3] output of the QuadSPI
module is driven to in the inactive state. Refer to
Driving Flash Control Signals in Single and Dual Mode .
0 IOFA[3] is driven to logic L
1 IOFA[3] is driven to logic H
16
ISD2FA
Idle Signal Drive IOFA[2] Flash A. This bit determines the logic level the IOFA[2] output of the QuadSPI
module is driven to in the inactive state. Refer to
Driving Flash Control Signals in Single and Dual Mode .
0 IOFA[2] is driven to logic L
1 IOFA[2] is driven to logic H
15
DOZE
Doze Enable. The DOZE bit provides support for externally controlled Doze Mode power-saving
mechanism.
0 A doze request will be ignored by the QuadSPI module
1 A doze request will be processed by the QuadSPI module
14
MDIS
Module Disable. The MDIS bit allows the clock to the non-memory mapped logic in the QuadSPI to be
stopped, putting the QuadSPI in a software controlled power-saving state.
0 Enable QuadSPI clocks.
1 Allow external logic to disable QuadSPI clocks.
13–12
Reserved
This field is reserved.
11
CLR_TXF
Clear TX FIFO/Buffer. Invalidates the TX Buffer content.
This is a self-clearing field.
0 No action.
1 Read and write pointers of the TX Buffer are reset to 0. QSPI_TBSR[TRCTR] is reset to 0.
10
CLR_RXF
Clear RX FIFO. Invalidates the RX Buffer.
This is a self-clearing field.
0 No action.
1 Read and write pointers of the RX Buffer are reset to 0. QSPI_RBSR[RDBFL] is reset to 0.
9
Reserved
This field is reserved.
8
VAR_LAT_EN
This field is used to enable variable latency feature in the controller. This field is valid for HyperRAM where
Data strobe acts as an output from the memory during the command and address (CA) cycles of a read or
Table continues on the next page...
Memory Map and Register Definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
842 NXP Semiconductors