NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1707 / 1761

• Ignores its Rx input pin and drives its Tx pin as recessive.
• Shuts down the clocks to the PE and CHI submodules
• Sets MCR[NOTRDY] and MCR[LPMACK].
The Bus Interface Unit continues to operate, enabling the CPU to access memory-
mapped registers, except the Rx Mailboxes Global Mask registers, the Rx Buffer 14
Mask register, the Rx Buffer 15 Mask register, the Rx FIFO Global Mask register. The
Rx FIFO Information register, the message buffers, the Rx Individual Mask registers, and
the reserved words within RAM may not be accessed when the module is in Disable
mode. Exiting from this mode is done by negating the MDIS bit by the CPU, which
causes the FlexCAN to request to resume the clocks and negate the LPMACK bit after
the CAN protocol engine recognizes the negation of disable mode requested by the CPU.
49.5.11.3 Stop mode
This is a system low-power mode in which all chip clocks can be stopped for maximum
power savings. The Stop mode is globally requested by the CPU and acknowledgement is
obtained through the assertion by the FlexCAN of a Stop Acknowledgement signal. The
CPU must only consider the FlexCAN in Stop mode when both request and
acknowledgement conditions are satisfied.
If FlexCAN receives the global Stop mode request during Freeze mode, it sets
MCR[LPMACK], negates MCR[FRZACK], and then sends the Stop Acknowledge
signal to the CPU, in order to shut down the clocks globally.
If Stop mode is requested during transmission or reception, FlexCAN does the following:
• Waits to be in either Idle or Bus Off state, or else waits for the third bit of
Intermission and checks it to be recessive
• Waits for all internal activities like arbitration, matching, move-in, and move-out to
finish. A pending move-in is not taken into account.
• Ignores its Rx input pin and drives its Tx pin as recessive
• Sets MCR[NOTRDY] and MCR[LPMACK]
• Sends a Stop Acknowledge signal to the CPU, so that it can shut down the clocks
globally
Stop mode is exited when the CPU resumes the clocks and removes the Stop mode
request.
After the CAN protocol engine recognizes the negation of the Stop mode request, the
FlexCAN negates MCR[LPMACK]. FlexCAN will then wait for 11 consecutive
recessive bits to synchronize to the CAN bus.
Chapter 49 FlexCAN
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1707