NXP Semiconductors MWCT101 S Series, Reference Manual

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• Accessing the MPU—Allocate a region descriptor to restrict MPU access to
supervisor mode from a specific master.
• Detecting an access error—The current bus cycle is terminated with an error
response and EARn and EDRn capture information on the faulting reference. The
error-terminated bus cycle typically initiates an error response in the originating bus
master. For example, a processor core may respond with a bus error exception, while
a data movement bus master may respond with an error interrupt. The processor can
retrieve the captured error address and detail information simply by reading
E{A,D}Rn. CESR[SPERR] signals which error registers contain captured fault data.
• Overlapping region descriptors—Applying overlapping regions often reduces the
number of descriptors required for a given set of access controls. In the overlapping
memory space, the protection rights of the corresponding region descriptors are
logically summed together (the boolean OR operator).
The following dual-core system example contains four bus masters:
• The two processors: CP0, CP1
• Two DMA engines: DMA1, a traditional data movement engine transferring data
between RAM and peripherals and DMA2, a second engine transferring data to/
from the RAM only
Consider the following region descriptor assignments:
Table 13-5. Overlapping region descriptor example
Region description RGDn CP0 CP1 DMA1 DMA2
CP0 code 0 rwx r-- — —
Flash
CP1 code 1 r-- rwx — —
CP0 data & stack 2 rw- — — —
RAM
CP0
→
CP1 shared data 2
3 r-- r-- — —
CP1
→
CP0 shared data 4
CP1 data & stack 4 — rw- — —
Shared DMA data 5 rw- rw- rw rw
MPU 6 rw- rw- — —
Peripheral
space
Peripherals 7 rw- rw- rw —
In this example, there are eight descriptors used to span nine regions in the three main
spaces of the system memory map: flash, RAM, and peripheral space. Each region
indicates the specific permissions for each of the four bus masters and this definition
provides an appropriate set of shared, private and executable memory spaces.
Of particular interest are the two overlapping spaces: region descriptors 2 & 3 and 3 & 4.
Chapter 13 Memory Protection Unit (MPU)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 235