NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1416 / 1761

46.3.1 LPI2C register descriptions
46.3.1.1 LPI2C Memory map
LPI2C0 base address: 4006_6000h
LPI2C1 base address: 4006_7000h
Offset Register Width
(In bits)
Access Reset value
0h Version ID Register (VERID) 32 RO 0100_0003h
4h Parameter Register (PARAM) 32 RO 0000_0202h
10h Master Control Register (MCR) 32 RW 0000_0000h
14h Master Status Register (MSR) 32 W1C 0000_0001h
18h Master Interrupt Enable Register (MIER) 32 RW 0000_0000h
1Ch Master DMA Enable Register (MDER) 32 RW 0000_0000h
20h Master Configuration Register 0 (MCFGR0) 32 RW 0000_0000h
24h Master Configuration Register 1 (MCFGR1) 32 RW 0000_0000h
28h Master Configuration Register 2 (MCFGR2) 32 RW 0000_0000h
2Ch Master Configuration Register 3 (MCFGR3) 32 RW 0000_0000h
40h Master Data Match Register (MDMR) 32 RW 0000_0000h
48h Master Clock Configuration Register 0 (MCCR0) 32 RW 0000_0000h
50h Master Clock Configuration Register 1 (MCCR1) 32 RW 0000_0000h
58h Master FIFO Control Register (MFCR) 32 RW 0000_0000h
5Ch Master FIFO Status Register (MFSR) 32 RO 0000_0000h
60h Master Transmit Data Register (MTDR) 32 WO 0000_0000h
70h Master Receive Data Register (MRDR) 32 RO 0000_4000h
110h Slave Control Register (SCR) 32 RW 0000_0000h
114h Slave Status Register (SSR) 32 W1C 0000_0000h
118h Slave Interrupt Enable Register (SIER) 32 RW 0000_0000h
11Ch Slave DMA Enable Register (SDER) 32 RW 0000_0000h
124h Slave Configuration Register 1 (SCFGR1) 32 RW 0000_0000h
128h Slave Configuration Register 2 (SCFGR2) 32 RW 0000_0000h
140h Slave Address Match Register (SAMR) 32 RW 0000_0000h
150h Slave Address Status Register (SASR) 32 RO 0000_4000h
154h Slave Transmit ACK Register (STAR) 32 RW 0000_0000h
160h Slave Transmit Data Register (STDR) 32 WO 0000_0000h
170h Slave Receive Data Register (SRDR) 32 RO 0000_4000h
Memory Map and Registers
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1416 NXP Semiconductors