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• and the HREQ pin is asserted (or disabled)
• and the LPSPI is enabled
• To perform the SPI bus transfer, LPSPI uses the attributes configured in the Transmit
Command Register (TCR) and uses the timing parameters in the Clock Configuration
Register (CCR).
• The SPI bus transfer ends after the FRAMESZ configuration is reached, or at the end
of a word when a new transmit command word is at the top of the transmit/command
FIFO.
• The HREQ input is only checked on the next time that the LPSPI goes idle (the
LPSPI completes the current transfer and the Transmit Command Register (TCR) is
empty).
Circular FIFO: The transmit/command FIFO also supports a Circular FIFO feature,
which enables the LPSPI master to (periodically) repeat a short data transfer that can fit
within the transmit/command FIFO, without requiring additional FIFO accesses. When
the circular FIFO is enabled, the current state of the FIFO read pointer is saved and the
status flags do not update. After the transmit/command FIFO is considered empty and the
LPSPI is idle, the FIFO read pointer is restored with the saved version, so the contents of
the transmit/command FIFO are not permanently pulled from the FIFO while circular
FIFO mode is enabled.
45.4.2.2 Receive FIFO and Data Match
The receive FIFO is used to store receive data during SPI bus transfers. When the
Receive Data Mask TCR[RXMSK] bit is set, the receive data is discarded instead of
being stored in the receive FIFO.
• The receive data is written to the receive FIFO at the end of the frame.
• During a multiple word or continuous transfer, the receive data is also written to the
receive FIFO at the same time as the new transmit data is read from the transmit
FIFO.
• During a continuous transfer, if the transmit FIFO is empty, then the receive data is
only written to the receive FIFO after the transmit FIFO is written or after the
Transmit Command Register (TCR) is written to end the frame.
Receive data supports a receive data match function that can match received data against
one of two words or against a masked data word. The receive data match function can
also be configured to compare only the first one or two received data words since the start
of the frame.
• Received data that is already discarded due to the Receive Data Mask TCR[RXMSK]
bit cannot cause the data match to set, and will delay the receive data match on the
first received data word, until all discarded data is received.
Chapter 45 Low Power Serial Peripheral Interface (LPSPI)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors
1401
Summary of Contents for MWCT101 S Series
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Page 50: ...Conventions MWCT101xS Series Reference Manual Rev 3 07 2019 50 NXP Semiconductors...
Page 70: ...Aliased bit band regions MWCT101xS Series Reference Manual Rev 3 07 2019 70 NXP Semiconductors...
Page 78: ...Pinout diagrams MWCT101xS Series Reference Manual Rev 3 07 2019 78 NXP Semiconductors...
Page 96: ...WCT101xS safety concept MWCT101xS Series Reference Manual Rev 3 07 2019 96 NXP Semiconductors...
Page 130: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 130 NXP Semiconductors...
Page 284: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 284 NXP Semiconductors...
Page 430: ...Functional Description MWCT101xS Series Reference Manual Rev 3 07 2019 430 NXP Semiconductors...
Page 472: ...Application Information MWCT101xS Series Reference Manual Rev 3 07 2019 472 NXP Semiconductors...
Page 528: ...Module clocks MWCT101xS Series Reference Manual Rev 3 07 2019 528 NXP Semiconductors...
Page 634: ...SRAM configuration MWCT101xS Series Reference Manual Rev 3 07 2019 634 NXP Semiconductors...
Page 818: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 818 NXP Semiconductors...
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Page 992: ...ADC calibration scheme MWCT101xS Series Reference Manual Rev 3 07 2019 992 NXP Semiconductors...
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Page 1726: ...Debug and security MWCT101xS Series Reference Manual Rev 3 07 2019 1726 NXP Semiconductors...
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