NXP Semiconductors MWCT101 S Series, Reference Manual

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41.5.13 PWM synchronization
The PWM synchronization provides an opportunity to update the MOD, HCR, CNTIN,
CnV, OUTMASK, INVCTRL and SWOCTRL registers with their buffered value and
force the FTM counter to the CNTIN register value.
Note
The legacy PWM synchronization (SYNCMODE = 0) is a
subset of the enhanced PWM synchronization (SYNCMODE =
1). Thus, only the enhanced PWM synchronization must be
used.
41.5.13.1 Hardware trigger
Three hardware trigger signal inputs of the FTM module are enabled when TRIGn = 1,
where n = 0, 1 or 2 corresponding to each one of the input signals, respectively. The
hardware trigger input n is synchronized by the FTM input clock. The PWM
synchronization with hardware trigger is initiated when a rising edge is detected at the
enabled hardware trigger inputs.
If (HWTRIGMODE = 0) then the TRIGn bit is cleared when 0 is written to it or when the
trigger n event is detected.
In this case, if two or more hardware triggers are enabled (for example, TRIG0 and
TRIG1 = 1) and only trigger 1 event occurs, then only TRIG1 bit is cleared. If a trigger n
event occurs together with a write setting TRIGn bit, then the synchronization is initiated,
but TRIGn bit remains set due to the write operation.
write 1 to TRIG0 bit
FTM input clock
synchronized trigger_0
by FTM input clock
trigger 0 event
Note
TRIG0 bit
trigger_0 input
All hardware trigger inputs have the same behavior.
Figure 41-52. Hardware trigger event with HWTRIGMODE = 0
Chapter 41 FlexTimer Module (FTM)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1223