NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 509 / 1761

Chapter 25
Clock Distribution
25.1 Introduction
This chapter presents the clock architecture overview of this device, clock distribution,
module clocks, and clock terminology. The System Clock Generator (SCG) module is
used to generate most of the clocks used by the device. The SCG module controls which
clock source (internal references, external crystals, external clocks) is used to derive
system clocks. The SCG also divides the selected clock source into a variety of clock
domains, including clocks for system bus masters, system bus slaves, and flash memory.
The clock generation circuitry provides several clock dividers and selectors allowing
different modules to be clocked at a frequency specific for that module. Clock generation
logic also implements module specific clock gating allowing modules to be individually
disabled. Thus, allowing optimization for performance or low power.
Various modules have specific clocks that can be generated from FIRC_CLK,
SIRC_CLK, SOSC_CLK, SPLL_CLK, or Power Management Controller (PMC) clock
signal (LPO128K_CLK). In addition, modules specific clocks that can be configured
from alternate sources. Clock selection for most modules is controlled by the PCC
module.
25.2 High level clocking diagram
The following diagram shows the high-level clocking architecture and various clock
sources for this device.
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 509