NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1393 / 1761

45.3.1.15.4 Fields
Field Function
31
CPOL
Clock Polarity
The Clock Polarity field is only updated between frames.
0b - The inactive state value of SCK is low
1b - The inactive state value of SCK is high
30
CPHA
Clock Phase
The Clock Phase field is only updated between frames.
0b - Data is captured on the leading edge of SCK and changed on the following edge of SCK
1b - Data is changed on the leading edge of SCK and captured on the following edge of SCK
29-27
PRESCALE
Prescaler Value
For all SPI bus transfers, the Prescaler value applied to the clock configuration register. The Prescaler
Value field is only updated between frames.
000b - Divide by 1
001b - Divide by 2
010b - Divide by 4
011b - Divide by 8
100b - Divide by 16
101b - Divide by 32
110b - Divide by 64
111b - Divide by 128
26
—
Reserved
25-24
PCS
Peripheral Chip Select
Configures the peripheral chip select used for the transfer. The Peripheral Chip Select field is only
updated between frames.
00b - Transfer using LPSPI_PCS[0]
01b - Transfer using LPSPI_PCS[1]
10b - Transfer using LPSPI_PCS[2]
11b - Transfer using LPSPI_PCS[3]
23
LSBF
LSB First
0b - Data is transferred MSB first
1b - Data is transferred LSB first
22
BYSW
Byte Swap
Byte swap will swap the contents of [31:24] with [7:0] and [23:16] with [15:8] for each transmit data word
read from the FIFO and for each received data word stored to the FIFO (or compared with match
registers).
0b - Byte swap is disabled
1b - Byte swap is enabled
21
CONT
Continuous Transfer
• In master mode, continuous transfer will keep the PCS asserted at the end of the frame size, until a
command word is received that starts a new frame.
• In slave mode, when continuous transfer is enabled, the LPSPI will only transmit the first
FRAMESZ bits; after which the LPSPI will transmit received data (assuming a 32-bit shift register).
0b - Continuous transfer is disabled
1b - Continuous transfer is enabled
20
CONTC
Continuing Command
Table continues on the next page...
Chapter 45 Low Power Serial Peripheral Interface (LPSPI)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1393