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to finish arbitration in Wait For Bus Idle state and the next state is Idle. In this case
the scan is not interrupted, and it is completed during Bus Idle state. During this
arbitration C/S write does not cause arbitration restart.
• Arbitration winner deactivation during a valid arbitration window.
• Upon exiting Freeze mode (first bit of the Wait For Bus Idle state). If there is a re-
synchronization during Wait For Bus Idle, the arbitration process is restarted.
Arbitration process stops in the following situations:
• All mailboxes were scanned.
• A Tx active mailbox is found if lowest buffer feature is enabled.
• Arbitration winner inactivation or abort during any arbitration process.
• There was not enough time to finish Tx arbitration process (for instance, when a
deactivation was performed near the end of frame). In this case arbitration process is
pending.
• Error or overload flag in the bus.
• Low Power or Freeze mode request in Idle state.
Arbitration is considered pending as described below:
• It was not possible to finish arbitration process in time.
• C/S write during arbitration if write is performed in a MB whose number is lower
than the Tx arbitration pointer.
• Any C/S write if there is no Tx arbitration process in progress.
• Rx Match has just updated a Rx code to Tx code.
• Entering Bus Off state.
C/S write during arbitration has the following effect:
• If C/S write is performed in the arbitration winner, a new process is restarted
immediately.
• If C/S write is performed in a MB whose number is higher than the Tx arbitration
pointer, the ongoing arbitration process will scan this MB as normal.
49.5.3 Receive process
To be able to receive CAN frames into a mailbox, the CPU must prepare it for reception
by executing the following steps:
1. If the mailbox is active (either Tx or Rx) inactivate the mailbox (see
), preferably with a safe inactivation (see
2. Write the ID word
Functional description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
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NXP Semiconductors
Summary of Contents for MWCT101 S Series
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Page 50: ...Conventions MWCT101xS Series Reference Manual Rev 3 07 2019 50 NXP Semiconductors...
Page 70: ...Aliased bit band regions MWCT101xS Series Reference Manual Rev 3 07 2019 70 NXP Semiconductors...
Page 78: ...Pinout diagrams MWCT101xS Series Reference Manual Rev 3 07 2019 78 NXP Semiconductors...
Page 96: ...WCT101xS safety concept MWCT101xS Series Reference Manual Rev 3 07 2019 96 NXP Semiconductors...
Page 130: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 130 NXP Semiconductors...
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Page 430: ...Functional Description MWCT101xS Series Reference Manual Rev 3 07 2019 430 NXP Semiconductors...
Page 472: ...Application Information MWCT101xS Series Reference Manual Rev 3 07 2019 472 NXP Semiconductors...
Page 528: ...Module clocks MWCT101xS Series Reference Manual Rev 3 07 2019 528 NXP Semiconductors...
Page 634: ...SRAM configuration MWCT101xS Series Reference Manual Rev 3 07 2019 634 NXP Semiconductors...
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Page 992: ...ADC calibration scheme MWCT101xS Series Reference Manual Rev 3 07 2019 992 NXP Semiconductors...
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Page 1726: ...Debug and security MWCT101xS Series Reference Manual Rev 3 07 2019 1726 NXP Semiconductors...
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