NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 900 / 1761

For AHB Commands, reads, starting from an address not aligned to 32 bit
boundaries, the requested bytes are given at the appropriate positions according to
the AMBA AHB specification.
• Buffer Entry Ordering for 64 Bit Read Access
For read access via the AHB interface 64 bit access is possible. Each 64 bit access
reads 2 32 bit entries simultaneously. The ordering of these 32 bit entries within the
64 bit word is given in the following table.
Table 33-17. 64 Bit Read Access Buffer Entry
Ordering
AHB Read Data Bit Position [63:0] [63:32] [31:0]
Buffer Entry # Odd (1, 3, 5, …) Even (0, 2, 4, …)
33.7.2.10 Normal Mode Interrupt and DMA Requests
The QuadSPI module has different flags that can only generate interrupt requests and one
flag that can generate interrupt as well as DMA requests. The following table lists the
eight conditions. Note that the flags mentioned in the table are related to the
Flag Register
(QSPI_FR) .
Table 33-18. Interrupt and DMA Request Conditions
Condition Flag(QSPI_FR) DMA
TX Buffer Fill TBFF -
TX Buffer Underrun TBUF -
Illegal Instruction Error ILLINE -
RX Buffer Drain RBDF X
RX Buffer Overflow RBOF -
AHB Buffer Overflow ABOF -
AHB Sequence Error ABSEF -
AHB Illegal Transaction Error AITEF -
AHB Illegal Burst Size Error AIBSEF -
IP Command Trigger during AHB
Access Error IPAEF -
IP Command Trigger could not be
executed Error IPIEF -
IP Command related Transaction
Finished TFF -
Functional Description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
900 NXP Semiconductors